Enhanced Host Controller Interface: Difference between revisions
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=== USB Status Register === |
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| 31-16 || Reserved || |
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| 15 || Async Schedule Status || |
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| 14 || Periodic Schedule Status || |
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| 13 || Reclamation || |
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| 12 || Halted || |
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| 11-6 || Reserved || |
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| 5 || Doorbell Interrupt || |
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| 4 || Host System Error || |
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| 3 || Frame List Rollover || |
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| 2 || Port Change Detect || |
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| 1 || USB Error Interrupt || |
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| 0 || USB Transfer Interrupt || |
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=== USB Interrupt Enable Register === |
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| 31-6|| Reserved || |
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| 5 || Async Advance Interrupt Enable || |
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| 4 || Host System Error Interrupt Enable || |
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| 3 || Frame List Rollover Interrupt Enable || |
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| 2 || Port Change Interrupt Enable || |
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| 1 || USB Error Interrupt Enable || |
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| 0 || USB Transfer Interrupt Enable || |
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Revision as of 03:30, 23 April 2017
EHCI (Enhanced Host Controller Interface) is the Single method of interfacing with USB 2.0. This makes life a lot easier than with USB 1.0, where 2 incompatible standards both survived. This is because the USB-IF insisted on a single implementation, produced by Intel.
Interface
On a PC you will normally find the EHCI USB controller on the PCI bus - in fact it is the only access method specified in the specification. USB 2.0 supports interfacing with USB 1.0 devices. However, EHCI is NOT expected to support them. Instead, you will find an UHCI or OHCI companion controller. Therefore you must implement OHCI and UHCI as well. Note there are NOT companions of both types, it is one type or another.
The EHCI controller will always have a PCI Class ID of 0x0C, a Subclass ID of 0x03, and an Interface value of 0x20. These values can be used to find the configuration space of the controller, which contains the memory mapped address of the EHCI registers. The address information can be found in the BAR0 PCI configuration space register.
Capability Registers
The capability registers can be found in memory at the address specified in the PCI configuration space BAR0 register.
| Offset (Hex) | Name | Description |
|---|---|---|
| 00 | CAPLENGTH | Capability Register Length |
| 01 | Reserved | |
| 02 | HCIVERSION | Interface Version Number (BCD) |
| 04 | HCSPARAMS | Structural Parameters |
| 08 | HCCPARAMS | Capability Parameters |
| 0C | HCSP-PORTROUTE | Companion Port Route Description |
Operation Registers
The operation registers can be found after the capability register area in memory. Add the Capability Register Length value above to the BAR0 address to find the operation register base address.
| Offset (Hex) | Name | Description |
|---|---|---|
| 00 | USBCMD | USB Command |
| 04 | USBSTS | USB Status |
| 08 | USBINTR | USB Interrupt Enable |
| 0C | FRINDEX | USB Frame Index |
| 10 | CTRLDSSEGMENT | 4G Segment Selector |
| 14 | PERIODICLISTBASE | Frame List Base Address |
| 18 | ASYNCLISTADDR | Next Asynchronous List Address |
| 40 | CONFIGFLAG | Configured Flag Register |
| 44 | PORTSC[1-N_PORTS] | Port Status/Control Register |
USB Command Register
| Bits | Name | Description |
|---|---|---|
| 31-24 | Reserved | |
| 23-16 | Interrupt Threshold | Number of micro frames to process between interrupts |
| 15-12 | Reserved | |
| 11 | Async Schedule Park Mode Enable | |
| 10 | Reserved | |
| 9-8 | Async Schedule Park Mode Count | |
| 7 | Light Host Controller Reset | Resets the controller without affecting connected devices |
| 6 | Interrupt On Async Advance Doorbell | Allows software to trigger interrupt |
| 5 | Async Schedule Enable | |
| 4 | Periodic Schedule Enable | |
| 3-2 | Programmable Frame List Size | |
| 1 | Host Controller Reset | |
| 0 | Run |
USB Status Register
| Bits | Name | Description |
|---|---|---|
| 31-16 | Reserved | |
| 15 | Async Schedule Status | |
| 14 | Periodic Schedule Status | |
| 13 | Reclamation | |
| 12 | Halted | |
| 11-6 | Reserved | |
| 5 | Doorbell Interrupt | |
| 4 | Host System Error | |
| 3 | Frame List Rollover | |
| 2 | Port Change Detect | |
| 1 | USB Error Interrupt | |
| 0 | USB Transfer Interrupt |
USB Interrupt Enable Register
| Bits | Name | Description |
|---|---|---|
| 31-6 | Reserved | |
| 5 | Async Advance Interrupt Enable | |
| 4 | Host System Error Interrupt Enable | |
| 3 | Frame List Rollover Interrupt Enable | |
| 2 | Port Change Interrupt Enable | |
| 1 | USB Error Interrupt Enable | |
| 0 | USB Transfer Interrupt Enable |