Detecting CPU Speed: Difference between revisions

using the following :

<pre>

prepare_a_timer(X milliseconds ahead);

cpuspeed_mhz = (iteration_counter * clock_cycles_per_iteration)/1000;

</pre>

Note that except for very special cases, using a busy-loop (even calibrated) to introduce delays is a bad idea and that it should be kept for very small delays

It is possible to create code which is exceptionally pipeline hostile such as:

<pre>

xor eax,edx

...

</pre>

A simple xor instruction takes one cycle, and it's guaranteed that the processor cannot pipeline this code as the current instructions operands depend on the results from the last calculation. One can check that, for a small count (tested from 16 to 64), RDTSC will show the instruction count is almost exactly (sometimes off by one) the cycles count. Unfortunately, when making the chain longer you'll start experiencing code cache misses, which will ruin the whole process.

* it's assumed that the command CPUID is supported.

<pre>

;__get_speed__:

mov ~[mhz], ax

</pre>

See the intel manual (see links) for more information.

I'd be tempted to say 'yes', though I haven't gave it a test nor heard of it elsewhere so far. Here is the trick:

<pre>

disable() // disable interrupts (if still not done)

byte hi=inb(0x40);

</pre>

Now, we know that

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