Detecting CPU Speed: Difference between revisions

It is possible to create code which is exceptionally pipeline hostile such as:

xor eax,edx

xor edx,eax

xor edx,eax

...

A simple xor instruction takes one cycle, which guarantees that the processor cannot pipeline this code as the current instructions operands depend on the results from the last calculation. One can check that, for a small count (tested from 16 to 64), RDTSC will show the instruction count is almost exactly (sometimes off by one) the cycles count. Unfortunately, when making the chain longer, code cache misses will occur, ruining the whole process.

I'd be tempted to say 'yes', though I haven't gave it a test nor heard of it elsewhere so far. Here is the trick:

disable() // disable interrupts (if still not done)

outb(0x43,0x34); // set PIT channel 0 to single-shot mode

byte lo=inb(0x40);

byte hi=inb(0x40);

Now, we know that