Detecting CPU Speed: Difference between revisions
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m →Working Example Code: fixed a bug where the code did not run when TSC was detected ('jnz detect_end' should have been 'jz detect_end') |
m →Knowing how many cycles your loop takes: Sourceification |
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It is possible to create code which is exceptionally pipeline hostile such as: |
It is possible to create code which is exceptionally pipeline hostile such as: |
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<source lang="asm"> |
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<pre> |
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xor eax,edx |
xor eax,edx |
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xor edx,eax |
xor edx,eax |
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xor edx,eax |
xor edx,eax |
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... |
... |
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</ |
</source> |
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A simple xor instruction takes one cycle, and it's guaranteed that the processor cannot pipeline this code as the current instructions operands depend on the results from the last calculation. One can check that, for a small count (tested from 16 to 64), RDTSC will show the instruction count is almost exactly (sometimes off by one) the cycles count. Unfortunately, when making the chain longer you'll start experiencing code cache misses, which will ruin the whole process. |
A simple xor instruction takes one cycle, and it's guaranteed that the processor cannot pipeline this code as the current instructions operands depend on the results from the last calculation. One can check that, for a small count (tested from 16 to 64), RDTSC will show the instruction count is almost exactly (sometimes off by one) the cycles count. Unfortunately, when making the chain longer you'll start experiencing code cache misses, which will ruin the whole process. |
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