Chip Numbers, Acronyms and Things: Difference between revisions
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;Expanded Memory:Memory used by an EMS driver. Located beyond 1mb mark. |
;Expanded Memory:Memory used by an EMS driver. Located beyond 1mb mark. |
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;Extended Memory:Memory used by an XMS driver. Located beyond the 1mb mark. The first 64kb of XMS is known as HMA (High Memory Area). |
;Extended Memory:Memory used by an XMS driver. Located beyond the 1mb mark. The first 64kb of XMS is known as HMA (High Memory Area). |
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;Fault:An exception that is |
;Fault:An exception that is recognized by the processor before the CPU executes the code. eg: trying to access memory swapped out to disk triggers a fault BEFORE the memory is accessed so it can be swapped into memory. |
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;FDC:Floppy Disk Controller |
;FDC:Floppy Disk Controller |
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;FIFO:First In First Out. FIFO buffers are common in newer UART chips for communications (16550AFN) |
;FIFO:First In First Out. FIFO buffers are common in newer UART chips for communications (16550AFN) |
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;PD765:The floppy controller chip in the XT |
;PD765:The floppy controller chip in the XT |
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;Multitasking:Where the CPU 'appears' to be running several tasks all at the same time. |
;Multitasking:Where the CPU 'appears' to be running several tasks all at the same time. |
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⚫ | |||
;Multitasking OS:The difference between unix and dos :> joke! see Multitasking. good examples of MOS and nonMOS are unix to dos, vms to cpm, etc. |
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;NMI:Non Maskable Interrupt. An interrupt request sent to the CPU that must be dealt with immediately. |
;NMI:Non Maskable Interrupt. An interrupt request sent to the CPU that must be dealt with immediately. |
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;Page:Section of memory that is classed as a single entity. eg: x86 in pmode has pages of 1byte, 4kb and 4mb in size. |
;Page:Section of memory that is classed as a single entity. eg: x86 in pmode has pages of 1byte, 4kb and 4mb in size. |
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;Page Directory:Holds the entries for the paging table mechanism. Unlike Page Tables, the Page Directory can't be swapped out of memory. |
;Page Directory:Holds the entries for the paging table mechanism. Unlike Page Tables, the Page Directory can't be swapped out of memory. |
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;PCI:Peripheral Component Interconnect. A Local Bus standard running at 32bits at 33mhz (can go higher). PCI has replaced ISA as the most common bus interface for |
;PCI:Peripheral Component Interconnect. A Local Bus standard running at 32bits at 33mhz (can go higher). PCI has replaced ISA as the most common bus interface for desktop computers. |
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;PCMCIA:Personal Computer Memory Card International Association. Small credit card sized units that plug into portable computer PCMCIA slot and provide things like extra memory, modems, etc. |
;PCMCIA:Personal Computer Memory Card International Association. Small credit card sized units that plug into portable computer PCMCIA slot and provide things like extra memory, modems, etc. |
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;PIC:Programmable Interrupt Controller. The PIC manages hardware interrupts. |
;PIC:Programmable Interrupt Controller. The PIC manages hardware interrupts. |
Revision as of 19:29, 13 February 2007
- 6845
- Graphics controller chip used in many many graphic adaptors
- 8042
- Controller chip in the AT keyboard
- 8048
- Controller chip in the XT keyboard
- 82072A
- Controller chip in the AT floppy disk drive
- 82077A
- Controller chip in PS2 floppy disk drive. Successor to the 82072A
- 82284
- The 80286 clock generator
- 82288
- The 80286 bus controller chip
- 8237A
- An 8bit DMA controller in the XT. Two chips in the AT and beyond, with four DMA channels per chip. Chips can be cascaded.
- 82450
- UART chip in the AT, successor to the 8250.
- 82489DX
- Advanced Programmable Interrupt Controller (APIC) in Pentiums and multiprocessor systems. The successor to the 8259A PIC.
- 8253
- Programmable Interval Timer (PIT) chip in the XT and AT. Has three independent timers.
- 8254
- Programmable Interval Timer (PIT). Used in AT's and EISA/MCA machines. Just an improved version of the 8253.
- 8259A
- Programmable Interrupt Controller (PIC) used in all PC's that predate Pentiums (Even many Pentiums and clones still use this instead of the APIC). Each chip has 8 interrupt lines. AT and beyond have two chips.
- 8284
- Clock generator in the 8088/8086/80186
- 8288
- Bus controller in the 8088/8086/80186
- 8741
- Common controller chip in AT keyboards
- 8742
- Controller chip in PS2 keyboards
- ABIOS
- Advanced BIOS. Refers to BIOS that support BIOS calls in Protected Mode.
- ARLL
- Advanced RLL. Method used in Hard Disks. MFM, RLL, etc.
- ASPI
- Advanced SCSI Programming Interface. An ADAPTEC thing, its a common interface for programming SCSI devices.
- ATA
- AT Attachment. Basically an IDE device (hd, cdrom, etc). Standards for connecting Hard Disks to an AT bus.
- BIST
- Built In Self Test.
- Booting
- The loading of the BIOS and kicking in the bootsector to bootstrap an OS loader.
- Bootstrap
- The bootstrap is a small program that loads an operating system. (Usually synonymous with the bootsector/MBR). Also used to describe the process of setting up a compiler on a new system not having one already.
- Bus Master
- Where a device can control the BUS autonomously. Examples of this are the CPU and DMA chips. Other controller chips can also do this (ala some PCI devices, etc).
- Call Gate
- Much like an software driven interrupt, a call gate allows access to other code from a different privilege level.
- Combicontroller
- Combine a Floppy disk controller chip and a Hard disk controller chip and you have a combicontroller. It is not limited to just floppy+hard drive chips. Usually meant to refer to the actual plug-in card where you have two floppy and two hd IDE ports.
- Descriptor
- An 8 byte structure that describes a segment/gate/task in protected mode.
- DMA
- Direct Memory Access. Allows peripheral devices to access main memory directly, bypassing the CPU.
- EISA
- Extended ISA. Basically extends the ISA bus from being 8bit to being 32bit. Designed for 386 + 486 systems.
- ESDI
- Enhanced Small Device Interface. A hard disk controlling mechanism. Successor to the ST506/412 interface. Can handle pumping data out at 24mbits (3mb a second)
- Exception
- CPU error. Usually hardware triggered, but can also be software triggered (some debug breakpoints, etc)
- Expanded Memory
- Memory used by an EMS driver. Located beyond 1mb mark.
- Extended Memory
- Memory used by an XMS driver. Located beyond the 1mb mark. The first 64kb of XMS is known as HMA (High Memory Area).
- Fault
- An exception that is recognized by the processor before the CPU executes the code. eg: trying to access memory swapped out to disk triggers a fault BEFORE the memory is accessed so it can be swapped into memory.
- FDC
- Floppy Disk Controller
- FIFO
- First In First Out. FIFO buffers are common in newer UART chips for communications (16550AFN)
- GDT
- Global Descriptor Table. This table contains descriptors that are potentially available to all programs in protected mode.
- HAL
- Hardware Abstraction Layer. Used by WindowsNT and some other operating systems. Lets NT "emulate" or "pretend" certain hardware exists even if not in your system.
- HDC
- Hard Disk Controller
- IDE
- Intelligent Drive Electronics. A standard for connecting hard disks, floppies, etc. to the AT bus.
- IDT
- Interrupt Descriptor Table. Table of 8byte entries that describe interrupts, traps, exceptions and fault handlers to the CPU.
- Interrupt
- Interrupts can be software or hardware generated. When an interrupt occurs, the CPU jumps to code assigned to be ran whenever that interrupt is triggered.
- Interrupt Gate
- A descriptor for calling an interrupt.
- IRQ
- Interrupt Request. Hardware signal to the CPU from an external peripheral.
- ISA
- Industry Standard Architecture. The defined BUS standard for AT's.
- LDT
- Local Descriptor Table. A table of descriptors that can only be accessed by the task that owns the LDT and none other.
- MC146818
- CMOS ram and Real Time Clock chip in the AT.
- MMU
- Memory Management Unit. The MMU is often contained within the CPU but can be external to the CPU. eg: old 68k CPU's did not have an MMU but one could be attached externally. The MMU is responsible for doing things like address segmentation translation and paging.
- PD765
- The floppy controller chip in the XT
- Multitasking
- Where the CPU 'appears' to be running several tasks all at the same time.
- Nibble,Nybble
- Group of 4 bits. Half a byte... Quarter a word... Eighth of a dword... etc..
- NMI
- Non Maskable Interrupt. An interrupt request sent to the CPU that must be dealt with immediately.
- Page
- Section of memory that is classed as a single entity. eg: x86 in pmode has pages of 1byte, 4kb and 4mb in size.
- Page Directory
- Holds the entries for the paging table mechanism. Unlike Page Tables, the Page Directory can't be swapped out of memory.
- PCI
- Peripheral Component Interconnect. A Local Bus standard running at 32bits at 33mhz (can go higher). PCI has replaced ISA as the most common bus interface for desktop computers.
- PCMCIA
- Personal Computer Memory Card International Association. Small credit card sized units that plug into portable computer PCMCIA slot and provide things like extra memory, modems, etc.
- PIC
- Programmable Interrupt Controller. The PIC manages hardware interrupts.
- PIT
- Programmable Interval Timer. The PIT is like a stopwatch with periodic alarm...
- POST
- Power On Self Test. Your computer does this when you turn it on in order to assess that its 100% A-OK and can boot up without error.
- RTC
- Real Time Clock
- SCSI
- Small Computer Systems Interface. A different method from ATA/IDE for connecting devices to your computer.
- Selector
- An index into a descriptor table.
- ST506/412
- Physical interface between a hard disk and computer.
- Task
- AKA a process or job. A task is just another program.
- Task Switch
- Changing from one task to another in an multi-tasking operating system.
- Trap
- An exception which occurs AFTER the error has occurred instead of before (see Fault).
- TSS
- Task State Segment. A data structure that holds the state of the CPU when for that task. Used by multitasking OS.
- Vesa Local Bus (VLB)
- BUS system for 386 and 486 machines. CPU speed specific.