CPU Registers x86: Difference between revisions

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====Control registers====
====Control registers====

======CR0======


{| {{wikitable}}
{| {{wikitable}}
|-
|-
! bit
| cr0
! label
| cr1
! description
| cr2
|-
| cr3
| cr4
| 0
| pe
| protected mode enable
|-
| 1
| mp
| monitor co-processor
|-
| 2
| em
| emulation
|-
| 3
| ts
| task switched
|-
| 4
| et
| extension type
|-
| 5
| ne
| numeric error
|-
| 16
| wp
| write protect
|-
| 18
| am
| alignment mask
|-
| 29
| nw
| not-write through
|-
| 30
| cd
| cache disable
|-
| 31
| pg
| paging
|-
|-
|}
|}


====Debug registers====
======CR1======

Reserved

======CR2======


{| {{wikitable}}
{| {{wikitable}}
|-
|-
! bit
| dr0
! label
| dr1
! description
| dr2
|-
| dr3
| dr4
| 0-31
| dr5
| pfla
| page fault linear address
| dr6
| dr7
|-
|-
|}
|}


====Test registers====
======CR3======


TODO

======CR4======


{| {{wikitable}}
{| {{wikitable}}
|-
|-
! bit
| tr3
! label
| tr4
! description
| tr5
|-
| tr6
| tr7
| 0
| vme
| virtual 8086 mode extensions
|-
| 1
| pvi
| protected mode virtual interrupts
|-
| 2
| tsd
| time stamp disable
|-
| 3
| de
| debugging extensions
|-
| 4
| pse
| page size extension
|-
| 5
| pae
| physical address extension
|-
| 6
| mce
| machine check exception
|-
| 7
| pge
| page global enable
|-
| 8
| pce
| performance monitoring counter enable
|-
| 9
| osfxsr
| os support for fxsave and fxrstor instructions
|-
| 10
| osxmmexcpt
| os support for unmasked simd floating point exceptions
|-
| 13
| vmxe
| virtual machine extensions enable
|-
| 14
| smxe
| safer mode extensions enable
|-
| 17
| pcide
| pcid enable
|-
| 18
| osxsave
| xsave and processor extended states enable
|-
| 20
| smep
| supervisor mode executions protection enable
|-
| 21
| smap
| supervisor mode access protection enable
|-
|-
|}
|}


====Pmode segmentation registers====
====Debug registers====


TODO

====Test registers====

TODO

====Pmode segmentation registers====


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Revision as of 19:10, 11 March 2015

CPU Registers are small amounts of memory located in the processor. They provide a fast way to process data.

x86 registers

General purpose registers

32 bit 16 bit 8 high bit 8 low bit description
eax ax ah al accumulator
ebx bx bh bl base
ecx cx ch cl counter
edx dx dh dl data

Segment registers

16 bit description
cs code segment
ds data segment
es, fs, gs extra segment
ss stack segment

Index registers

32 bit 16 bit description
esi si source index
edi di destination index

Pointer registers

32 bit 16 bit description
ebp bp base pointer
esp sp stack pointer
eip ip index pointer

EFLAGS register

bit label description
0 cf carry flag
2 pf parity flag
4 af auxiliary flag
6 zf zero flag
7 sf sign flag
8 tf trap flag
9 if interrupt flag
10 df direction flag
11 of overflow flag
12-13 iopl i/o priviledge level
14 nt nested task flag
16 rf resume flag
17 vm virtual 8086 mode flag
18 ac alignment check flag
19 vif virtual interrupt flag
20 vip virtual interrupt pending
21 id id flag

Control registers

CR0
bit label description
0 pe protected mode enable
1 mp monitor co-processor
2 em emulation
3 ts task switched
4 et extension type
5 ne numeric error
16 wp write protect
18 am alignment mask
29 nw not-write through
30 cd cache disable
31 pg paging
CR1

Reserved

CR2
bit label description
0-31 pfla page fault linear address
CR3

TODO

CR4
bit label description
0 vme virtual 8086 mode extensions
1 pvi protected mode virtual interrupts
2 tsd time stamp disable
3 de debugging extensions
4 pse page size extension
5 pae physical address extension
6 mce machine check exception
7 pge page global enable
8 pce performance monitoring counter enable
9 osfxsr os support for fxsave and fxrstor instructions
10 osxmmexcpt os support for unmasked simd floating point exceptions
13 vmxe virtual machine extensions enable
14 smxe safer mode extensions enable
17 pcide pcid enable
18 osxsave xsave and processor extended states enable
20 smep supervisor mode executions protection enable
21 smap supervisor mode access protection enable

Debug registers

TODO

Test registers

TODO

Pmode segmentation registers

gdtr global descriptor table register
idtr interrupt descriptor table register
ldtr local descriptor table register
tr task register