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CPU Registers x86: Difference between revisions
→DR7
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====DR7====
The low order 8 bits enable the four breakpoints. Bit 0 enables breaking at DR0 locally, Bit 1 enables a global breakpoint on DR0, Bit 2,3 for DR1 and so on.
A local breakpoint bit deactivates on hardware task switches, globals do not. Bits 16-17 determine conditions for DR0, 20-21 for DR1, 24-25 for DR2 and 28-29 for DR3. In these bits, 00b means execution break, 01b means a write watchpoint, and 11b means an R/W watchpoint. 10b is reserved for I/O R/W (unsupported). Bits 18-19 determine the size of the DR0 breakpoint, 22-23 for DR1, 26-27 for DR2 and 30-31 for DR3. TODO
==Test registers==
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