CPU Registers x86: Difference between revisions

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More info about gdtr and debug registers
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CPU Registers are small amounts of memory located in the processor. They provide a fast way to process data.
CPU Registers are small amounts of memory located in the processor. They provide a fast way to process data.


==x86 registers==
==General purpose registers==

⚫
====General purpose registers====


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====Segment registers====
==Segment registers==


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====Index registers====
==Index registers==


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====Pointer registers====
==Pointer registers==


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====EFLAGS register====
==EFLAGS register==


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====Control registers====
==Control registers==


======CR0======
====CR0====


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======CR1======
====CR1====


Reserved
Reserved


======CR2======
====CR2====


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======CR3======
====CR3====


CR3 contains the '''Physical''' Base Address of the Page Directory. In [[PAE]] mode, it is the base of the PDPT, and in [[Long Mode]] the PML4T.
It contains the Physical Base Address of the Page Directory. In [[PAE]] mode, it is the base of the PDPT, and in [[Long Mode]] the PML4T.
Note that this must be page aligned.
Note that this must be page aligned.


======CR4======
====CR4====


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====Debug registers====
==Debug registers==


⚫
====DR0 - DR3====
DR0 - DR3 are '''linear''' addresses of up to 4 breakpoints.
⚫
Dr7 controls breakpoint conditions - TODO


Contain linear addresses of up to 4 breakpoints. If paging is enabled, they are translated to physical addresses.
⚫
====Test registers====


====DR6====
⚫
TODO


It permits the debugger to determine which debug conditions have occured. When an enabled debug exception is enabled, low order bits 0-3 and set before entering debug exception handler.
⚫
====Pmode segmentation registers====

====DR7====

⚫
It controls breakpoint conditions - TODO

⚫
==Test registers==


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|-
|-
! name
| gdtr
! description
| global descriptor table register
|-
|-
| TR3 - TR5
| idtr
| undocumented
| interrupt descriptor table register
|-
|-
| ldtr
| TR6
| local descriptor table register
| test command register
|-
|-
| tr
| TR7
| task register
| test data register
|-
|-
|}
|}

⚫
==Pmode segmentation registers==

====GDTR====

{| {{wikitable}}
|-
! bits
! label
! description
|-
| 0-15
| limit
| size of [[GDT]]
|-
| 16-47
| base
| starting address of GDT
|-
|}

====LDTR====

⚫
TODO

====IDTR====

TODO

Revision as of 10:44, 13 March 2015

CPU Registers are small amounts of memory located in the processor. They provide a fast way to process data.

General purpose registers

32 bit 16 bit 8 high bit 8 low bit description
eax ax ah al accumulator
ebx bx bh bl base
ecx cx ch cl counter
edx dx dh dl data

Segment registers

16 bit description
cs code segment
ds data segment
es, fs, gs extra segment
ss stack segment

Index registers

32 bit 16 bit description
esi si source index
edi di destination index

Pointer registers

32 bit 16 bit description
ebp bp base pointer
esp sp stack pointer
eip ip index pointer

EFLAGS register

bit label description
0 cf carry flag
2 pf parity flag
4 af auxiliary flag
6 zf zero flag
7 sf sign flag
8 tf trap flag
9 if interrupt flag
10 df direction flag
11 of overflow flag
12-13 iopl i/o priviledge level
14 nt nested task flag
16 rf resume flag
17 vm virtual 8086 mode flag
18 ac alignment check flag
19 vif virtual interrupt flag
20 vip virtual interrupt pending
21 id id flag

Control registers

CR0

bit label description
0 pe protected mode enable
1 mp monitor co-processor
2 em emulation
3 ts task switched
4 et extension type
5 ne numeric error
16 wp write protect
18 am alignment mask
29 nw not-write through
30 cd cache disable
31 pg paging

CR1

Reserved

CR2

bit label description
0-31 pfla page fault linear address

CR3

It contains the Physical Base Address of the Page Directory. In PAE mode, it is the base of the PDPT, and in Long Mode the PML4T. Note that this must be page aligned.

CR4

bit label description
0 vme virtual 8086 mode extensions
1 pvi protected mode virtual interrupts
2 tsd time stamp disable
3 de debugging extensions
4 pse page size extension
5 pae physical address extension
6 mce machine check exception
7 pge page global enable
8 pce performance monitoring counter enable
9 osfxsr os support for fxsave and fxrstor instructions
10 osxmmexcpt os support for unmasked simd floating point exceptions
13 vmxe virtual machine extensions enable
14 smxe safer mode extensions enable
17 pcide pcid enable
18 osxsave xsave and processor extended states enable
20 smep supervisor mode executions protection enable
21 smap supervisor mode access protection enable

Debug registers

DR0 - DR3

Contain linear addresses of up to 4 breakpoints. If paging is enabled, they are translated to physical addresses.

DR6

It permits the debugger to determine which debug conditions have occured. When an enabled debug exception is enabled, low order bits 0-3 and set before entering debug exception handler.

DR7

It controls breakpoint conditions - TODO

Test registers

name description
TR3 - TR5 undocumented
TR6 test command register
TR7 test data register

Pmode segmentation registers

GDTR

bits label description
0-15 limit size of GDT
16-47 base starting address of GDT

LDTR

TODO

IDTR

TODO

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