It permits the debugger to determine which debug conditions have occured. When an enabled debug exception is enabled, low order bits 0-3 andare set before entering debug exception handler.
====DR7====
Revision as of 08:16, 15 March 2015
CPU Registers are small amounts of memory located in the processor. They provide a fast way to process data.
It contains the Physical Base Address of the Page Directory. In PAE mode, it is the base of the PDPT, and in Long Mode the PML4T.
Note that this must be page aligned.
CR4
bit
label
description
0
vme
virtual 8086 mode extensions
1
pvi
protected mode virtual interrupts
2
tsd
time stamp disable
3
de
debugging extensions
4
pse
page size extension
5
pae
physical address extension
6
mce
machine check exception
7
pge
page global enable
8
pce
performance monitoring counter enable
9
osfxsr
os support for fxsave and fxrstor instructions
10
osxmmexcpt
os support for unmasked simd floating point exceptions
13
vmxe
virtual machine extensions enable
14
smxe
safer mode extensions enable
17
pcide
pcid enable
18
osxsave
xsave and processor extended states enable
20
smep
supervisor mode executions protection enable
21
smap
supervisor mode access protection enable
Debug registers
DR0 - DR3
Contain linear addresses of up to 4 breakpoints. If paging is enabled, they are translated to physical addresses.
DR6
It permits the debugger to determine which debug conditions have occured. When an enabled debug exception is enabled, low order bits 0-3 are set before entering debug exception handler.
DR7
DR7 controls breakpoint conditions.
The low order 8 bits enable the four breakpoints. Bit 0 enables breaking at DR0 locally, Bit 1 enables a global breakpoint on DR0, Bit 2,3 for DR1 and so on.
A local breakpoint bit deactivates on hardware task switches, globals do not. Bits 16-17 determine conditions for DR0, 20-21 for DR1, 24-25 for DR2 and 28-29 for DR3. In these bits, 00b means execution break, 01b means a write watchpoint, and 11b means an R/W watchpoint. 10b is reserved for I/O R/W (unsupported). Bits 18-19 determine the size of the DR0 breakpoint, 22-23 for DR1, 26-27 for DR2 and 30-31 for DR3. TODO