BCM System Timer: Difference between revisions
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The free running counter is driven by the timer clock and stopped whenever the processor is stopped in debug mode. |
The free running counter is driven by the timer clock and stopped whenever the processor is stopped in debug mode. |
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The periperal's address is MMIO_BASE + 0x3000, which is 0x20003000 for older models, and 0x3F003000 on |
The periperal's address is MMIO_BASE + 0x3000, which is 0x20003000 for older models, and 0x3F003000 on ARM Quad Cores, RPi2 and upwards. |
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This timer operates on a fixed 1MHz frequency. |
This timer operates on a fixed 1MHz frequency. |
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[[Category:ARM]] |
[[Category:ARM]] |
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[[Category:Timers]] |
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Latest revision as of 14:52, 10 July 2023
Introduction
The BCM System Timer is a very simple, easy to use timer found on BCM2835-BCM2837 SoC (all Raspberry Pis, from Zero to 3B+). This peripheral provides four 32-bit timer channels and a single 64-bit free running counter. Each channel has an output compare register, which is compared against the 32 least significant bits of the free running counter values. When the two values match, the system timer peripheral generates a signal to indicate a match for the appropriate channel. The match signal is then fed into the interrupt controller. The interrupt service routine then reads the output compare register and adds the appropriate offset for the next timer tick. The free running counter is driven by the timer clock and stopped whenever the processor is stopped in debug mode.
The periperal's address is MMIO_BASE + 0x3000, which is 0x20003000 for older models, and 0x3F003000 on ARM Quad Cores, RPi2 and upwards.
This timer operates on a fixed 1MHz frequency.
See Also
External Links
- ARM Peripherals Section 12, Page 172