ATA PIO Mode: Difference between revisions
Jump to navigation
Jump to search
| [unchecked revision] | [unchecked revision] |
Content deleted Content added
m Fixed some grammar errors. |
Replaced a couple of pre tags with wikitables. |
||
| Line 121: | Line 121: | ||
===Registers=== |
===Registers=== |
||
An ATA bus typically has 9 |
An ATA bus typically has 9 I/O ports that control its behavior. For the primary bus, these I/O ports are 0x1F0 through 0x1F7, and 0x3F6 (see the directions below for usage details). The values in this table are relative to the so-called I/O port base address. So a port value of 1 actually means 0x1F0 + 1 = 0x1F1. This is done because the base address may vary depending on the hardware. |
||
<pre> |
|||
Port Function |
|||
0x1F0 Data port -- read and write PIO <b>data</b> bytes on this port |
|||
0x1F1 Features / Error info -- mostly used with ATAPI |
|||
0x1F2 Sector Count -- number of sectors to read/write (0 = special value) |
|||
0x1F3 Partial Disk Sector address (CHS / LBA28 / LBA48 specific) |
|||
0x1F4 Partial Disk Sector address |
|||
0x1F5 Partial Disk Sector address |
|||
0x1F6 Drive Select bit, Flag bits, Extra address bits |
|||
0x1F7 Command port / Regular Status port -- write commands / read status |
|||
</pre> |
|||
{| {{wikitable}} |
|||
====Status Byte bit definitions:==== |
|||
|- |
|||
! Port Offset |
|||
! Function |
|||
! Description |
|||
|- |
|||
| 0 |
|||
| Data Port |
|||
| Read/Write PIO '''data''' bytes on this port. |
|||
|- |
|||
| 1 |
|||
| Features / Error Information |
|||
| Usually used for ATAPI devices. |
|||
|- |
|||
| 2 |
|||
| Sector Count |
|||
| Number of sectors to read/write (0 is a special value). |
|||
|- |
|||
| 3 |
|||
| Sector Number |
|||
| This is CHS / LBA28 / LBA48 specific. |
|||
|- |
|||
| 4 |
|||
| Cylinder Low |
|||
| Partial Disk Sector address. |
|||
|- |
|||
| 5 |
|||
| Cylinder High |
|||
| Partial Disk Sector address. |
|||
|- |
|||
| 6 |
|||
| Drive / Head Port |
|||
| Used to select a drive and/or head. May supports extra address/flag bits. |
|||
|- |
|||
| 7 |
|||
| Command port / Regular Status port |
|||
| Used to send commands or read the current status. |
|||
|- |
|||
|} |
|||
====Status Byte==== |
|||
<pre>Bit Abbreviation Function |
|||
In the following table you will find the layout of the so-called Status Byte. |
|||
7 BSY Drive is preparing to accept/send data -- wait until this bit clears. If it never |
|||
clears, do a Software Reset. Technically, when BSY is set, the other bits in the |
|||
{| {{wikitable}} |
|||
Status byte are meaningless. |
|||
|- |
|||
6 RDY Bit is clear when drive is spun down, or after an error. Set otherwise. |
|||
! Bit |
|||
5 DF Drive Fault Error (does not set ERR!) |
|||
! Abbreviation |
|||
4 SRV Overlapped Mode Service Request |
|||
! Function |
|||
3 DRQ Set when the drive has PIO data to transfer, or is ready to accept PIO data. |
|||
|- |
|||
0 ERR Error flag (when set). Send a new command to clear it (or nuke it with a Software |
|||
| 0 |
|||
Reset). |
|||
| ERR |
|||
</pre> |
|||
| Indicates an error occurred. Send a new command to clear it (or nuke it with a Software Reset). |
|||
It is a Bad Idea to test the "Seek Complete" (DSC) bit -- it has been deprecated and reused for another purpose. |
|||
|- |
|||
| 3 |
|||
| DRQ |
|||
| Set when the drive has PIO data to transfer, or is ready to accept PIO data. |
|||
|- |
|||
| 4 |
|||
| SRV |
|||
| Overlapped Mode Service Request. |
|||
|- |
|||
| 5 |
|||
| DF |
|||
| Drive Fault Error ('''does not set ERR'''). |
|||
|- |
|||
| 6 |
|||
| RDY |
|||
| Bit is clear when drive is spun down, or after an error. Set otherwise. |
|||
|- |
|||
| 7 |
|||
| BSY |
|||
| Indicates the drive is preparing to send/receive data (wait for it to clear). In case of 'hang' (it never clears), do a software reset. |
|||
|} |
|||
Technically, when BSY is set, the other bits in the Status byte are meaningless. It is also generally a Bad Idea to test the "Seek Complete" (DSC) bit, because it has been deprecated and reused for another purpose. |
|||
====Device Control Register / Alternate Status==== |
====Device Control Register / Alternate Status==== |
||
| Line 157: | Line 207: | ||
=====Control Register bit definitions:===== |
=====Control Register bit definitions:===== |
||
<pre>Bit Abbreviation Function |
|||
{| {{wikitable}} |
|||
7 HOB Set this to read back the High Order Byte of the last LBA48 value sent to an IO port. |
|||
|- |
|||
2 SRST Software Reset -- set this to reset all ATA drives on a bus, if one is misbehaving. |
|||
! Bit |
|||
1 nIEN Set this to stop the current device from sending interrupts. |
|||
! Abbreviation |
|||
</pre> |
|||
! Function |
|||
All other bits are reserved and should always be clear. |
|||
|- |
|||
In general, you will want to leave HOB, SRST, and nIEN cleared. Set each Device Control Register to 0 once, during boot. |
|||
| 1 |
|||
| nIEN |
|||
| Set this to stop the current device from sending interrupts. |
|||
|- |
|||
| 2 |
|||
| SRST |
|||
| Set this to do a "Software Reset" on all ATA drives on a bus, if one is misbehaving. |
|||
|- |
|||
| 7 |
|||
| HOB |
|||
| Set this to read back the High Order Byte of the last LBA48 value sent to an IO port. |
|||
|} |
|||
All other bits are reserved and should always be clear. In general, you will want to leave HOB, SRST, and nIEN cleared. Set each Device Control Register to 0 once, during boot. |
|||
==Resetting a drive / Software Reset== |
==Resetting a drive / Software Reset== |
||