ARM Overview: Difference between revisions

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specified in parenthesis which is SP, LR, and PC. So using the mnemonic R15
specified in parenthesis which is SP, LR, and PC. So using the mnemonic R15
is the same as using the mnemonic PC, but keep in mind that this is only relevant to the assembler/compiler. The ARM processor only understands the value given using 4 bits in most instructions. The exactly value represented
is the same as using the mnemonic PC, but keep in mind that this is only relevant to the assembler/compiler. The ARM processor only understands the value given using 4 bits in most instructions. The exactly value represented
using these 4 bits for each mnemonic can be gained by simply removing the prefixed letter R. So that R5 is represented by 4 bits as 0101, R6 as 0110, and R7 as 0111. The denotation which postfix ''IRQ'', ''UNDEF'', ''ABT'', ''SVC'', and ''FIQ'' is simply for display; is relevant only to this table and are not considered valid with any assembler/compiler. For example ''R13ABT'', ''R13IRQ'', ''R13UNDEF'', ''R13SVC'', and ''R13FIQ'' all simply show that
using these 4 bits for each mnemonic can be gained by simply removing the prefixed letter R. So that R5 is represented by 4 bits as 0101, R6 as 0110, and R7 as 0111. The denotations that postfix ''IRQ'', ''UNDEF'', ''ABT'', ''SVC'', and ''FIQ'' are simply for display, and are relevant only to this table, and aren't considered valid by any assembler/compiler. For example ''R13ABT'', ''R13IRQ'', ''R13UNDEF'', ''R13SVC'', and ''R13FIQ'' all simply show that
internally the processor maps R13 (SP) to a different address in it's register file.
internally the processor maps R13 (SP) to a different address in it's register file.