Anonymous user
APIC: Difference between revisions
→Local APIC and IO-APIC: use internet archive link as the file is now missing
| [unchecked revision] | [unchecked revision] |
m (Added extra information to Logical Mode (cluster model is outdated)) |
(→Local APIC and IO-APIC: use internet archive link as the file is now missing) |
||
Line 15:
Each interrupt pin is individually programmable as either edge or level triggered. The interrupt vector and interrupt steering information can be specified per interrupt. An indirect register accessing scheme optimizes the memory space needed to access the I/O APIC's internal registers. To increase system flexibility when assigning memory space usage, the I/O APIC's two-register memory space is relocatable, but defaults to 0xFEC00000.
The Intel standards for the APIC can be found on the Intel site under the category "Multiprocessor Specification", or simply [http://web.archive.org/web/20070112195752/http://developer.intel.com/design/pentium/datashts/24201606.pdf this PDF file].
== Inter-Processor Interrupts ==
| |||