APIC: Difference between revisions

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the 14th and 15th Interrupt Command Register bits have been mixed up; see Volume 3A:System Programming Guide, Chapter 10.6.1
m Reverted edits by Nudelerde (talk) to last revision by Sebastian
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|-
| Bit 14
| Bit 14
| Clear for INIT level de-assert, otherwise set.
| Level. 0 = De-assert, 1 = Assert (only 1 for INIT de-assert)
|-
|-
| Bit 15
| Bit 15
| Trigger Mode. 0 = Edge, 1 = Level (only 1 for INIT assert and de-assert)
| Set for INIT level de-assert, otherwise clear.
|-
|-
| Bits 18-19
| Bits 18-19
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