APIC: Difference between revisions

[unchecked revision]

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@@ Line 42: / Line 42: @@
  *  note that this requires CPUID to be supported.
  */
-bool cpuHasAPIC()
+bool check_apic() {
-{
    uint32_t eax, edx;
    cpuid(1, &eax, &edx);
@@ Line 50: / Line 49: @@
 /* Set the physical address for local APIC registers */
-void cpuSetAPICBase(uintptr_t apic)
+void cpu_set_apic_base(uintptr_t apic) {
-{
    uint32_t edx = 0;
    uint32_t eax = (apic & 0xfffff100) | IA32_APIC_BASE_MSR_ENABLE;
@@ Line 59: / Line 57: @@
 #endif
-   cpuSetMSR(IA32_APIC_BASE_MSR, eax, edx);
+   cpu_set_msr(IA32_APIC_BASE_MSR, eax, edx);
 }
@@ Line 66: / Line 64: @@
  * make sure you map it to virtual memory ;)
  */
-uintptr_t cpuGetAPICBase()
+uintptr_t cpu_get_acpi_base() {
-{
    uint32_t eax, edx;
-   cpuGetMSR(IA32_APIC_BASE_MSR, &eax, &edx);
+   cpu_get_msr(IA32_APIC_BASE_MSR, &eax, &edx);
 #ifdef __PHYSICAL_MEMORY_EXTENSION__
@@ Line 78: / Line 75: @@
 }
-void enableAPIC()
+void enable_apic() {
-{
     /* Hardware enable the Local APIC if it wasn't enabled */
-    cpuSetAPICBase(cpuGetAPICBase());
+    cpu_set_apic_base(cpuGetAPICBase());
     /* Set the Spourious Interrupt Vector Register bit 8 to start receiving interrupts */
-    WriteRegister(0xF0, ReadRegister(0xF0) | 0x100);
+    write_reg(0xF0, ReadRegister(0xF0) | 0x100);
 }
 </source>

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