APIC: Difference between revisions
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m Used MSR functions that actually exist |
Added table of LAPIC registers. Table taken from the x86 sdm (Volume 3A, Chapter 10.4) |
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== Local APIC registers == |
== Local APIC registers == |
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The local APIC registers are memory mapped to an address that can be found in the MP/MADT tables. Make sure you map these to virtual memory if you are using paging. Each register is 32 bits long, and expects to be written and read as a 32 bit integer. Although each register is 4 bytes, they are all aligned on a 16 byte boundary. |
The local APIC registers are memory mapped to an address that can be found in the MP/MADT tables. Make sure you map these to virtual memory if you are using paging. Each register is 32 bits long, and expects to be written and read as a 32 bit integer. Although each register is 4 bytes, they are all aligned on a 16 byte boundary. |
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List of local APIC registers (TODO: Add descriptions for all registers): |
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{| {{wikitable}} |
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|- |
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| Offset |
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| Register name |
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| Read/Write permissions |
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|- |
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|- |
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| 000h - 010h |
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| Reserved |
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| |
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|- |
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| 020h |
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| LAPIC ID Register |
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| Read/Write |
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|- |
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|- |
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| 030h |
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| LAPIC Version Register |
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| Read only |
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|- |
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|- |
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| 040h - 070h |
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| Reserved |
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| |
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|- |
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|- |
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| 080h |
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| Task Priority Register (TPR) |
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| Read/Write |
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|- |
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|- |
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| 090h |
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| Arbitration Priority Register (APR) |
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| Read only |
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|- |
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|- |
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| 0A0h |
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| Processor Priority Register (PPR) |
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| Read only |
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|- |
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|- |
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| 0B0h |
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| EOI register |
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| Write only |
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|- |
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|- |
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| 0C0h |
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| Remote Read Register (RRD) |
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| Read only |
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|- |
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|- |
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| 0D0h |
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| Logical Destination Register |
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| Read/Write |
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|- |
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|- |
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| 0E0h |
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| Destination Format Register |
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| Read/Write |
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|- |
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|- |
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| 0F0h |
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| Spurious Interrupt Vector Register |
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| Read/Write |
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|- |
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|- |
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| 100h - 170h |
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| In-Service Register (ISR) |
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| Read only |
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|- |
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|- |
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| 180h - 1F0h |
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| Trigger Mode Register (TMR) |
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| Read only |
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|- |
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| 200h - 270h |
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| Interrupt Request Register (IRR) |
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| Read only |
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|- |
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|- |
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| 280h |
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| Error Status Register |
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| Read only |
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|- |
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|- |
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| 290h - 2E0h |
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| Reserved |
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| |
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|- |
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|- |
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| 2F0h |
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| LVT Corrected Machine Check Interrupt (CMCI) Register |
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| Read/Write |
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|- |
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|- |
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| 300h - 310h |
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| Interrupt Command Register (ICR) |
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| Read/Write |
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|- |
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|- |
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| 320h |
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| LVT Timer Register |
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| Read/Write |
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|- |
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|- |
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| 330h |
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| LVT Thermal Sensor Register |
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| Read/Write |
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|- |
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|- |
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| 340h |
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| LVT Performance Monitoring Counters Register |
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| Read/Write |
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|- |
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|- |
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| 350h |
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| LVT LINT0 Register |
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| Read/Write |
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|- |
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|- |
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| 360h |
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| LVT LINT1 Register |
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| Read/Write |
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|- |
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|- |
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| 370h |
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| LVT Error Register |
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| Read/Write |
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|- |
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|- |
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| 380h |
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| Initial Count Register (for Timer) |
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| Read/Write |
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|- |
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|- |
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| 390h |
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| Current Count Register (for Timer) |
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| Read only |
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|- |
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|- |
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| 3A0h - 3D0h |
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| Reserved |
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| |
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|- |
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|- |
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| 3E0h |
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| Divide Configuration Register (for Timer) |
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| Read/Write |
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|- |
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|- |
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| 3F0h |
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| Reserved |
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| |
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|- |
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|} |
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=== EOI Register === |
=== EOI Register === |
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* [http://developer.intel.com/design/chipsets/specupdt/290710.htm updated I/O APIC specification/datasheet] |
* [http://developer.intel.com/design/chipsets/specupdt/290710.htm updated I/O APIC specification/datasheet] |
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* [http://www.intel.com/products/processor/manuals/ Volume 3A:System Programming Guide, Part 1,manuals has a chapter on the APIC] |
* [http://www.intel.com/products/processor/manuals/ Volume 3A:System Programming Guide, Part 1,manuals has a chapter on the APIC] |
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* [http://www.intel.com/products/processor/manuals/ Volume 3A:System Programming Guide, Chapter 10.4 for further reading about the LAPIC] |
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* [http://web.archive.org/web/20140308064246/http://www.osdever.net/tutorials/pdf/apic.pdf Advanced Programmable Interrupt Controller by Mike Rieker] |
* [http://web.archive.org/web/20140308064246/http://www.osdever.net/tutorials/pdf/apic.pdf Advanced Programmable Interrupt Controller by Mike Rieker] |
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* [http://web.archive.org/web/20100918084750/http://www.microsoft.com/whdc/archive/apic.mspx "The Importance of Implementing APIC-Based Interrupt Subsystems on Uniprocessor PCs". Microsoft. 18 September 2010] |
* [http://web.archive.org/web/20100918084750/http://www.microsoft.com/whdc/archive/apic.mspx "The Importance of Implementing APIC-Based Interrupt Subsystems on Uniprocessor PCs". Microsoft. 18 September 2010] |