X86-64 Instruction Encoding: Difference between revisions

→‎VEX/XOP opcodes: Better layout
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(→‎VEX/XOP opcodes: Better layout)
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There are many VEX and XOP instructions, all of which can be encoded using the three byte VEX/XOP escape prefix. The VEX and XOP escape prefixes use fields with the following semantics:
 
{| {{wikitable|background-color:white;}}
!style="background-color:#f9f9f9;"| Field
! Field
!style="background-color:#f9f9f9;"| Length
! Length
!style="background-color:#f9f9f9;"| Description
|-
!style="background-color:#f9f9f9; text-align: left; vertical-align: top;"| VEX/XOP prefix
| VEX/XOP prefix||8 bits||Prefix.
|style="vertical-align: top;"|8 bits||Prefix.
{| {{wikitable}}
! Prefix
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|}
|-
!style="background-color:#f9f9f9; text-align: left; vertical-align: top;"| ~R
|style="vertical-align: ~R|top;"|1 bit||This 1-bit value is an 'inverted' extension to the ''MODRM.reg'' field. The inverse of REX.R. See [[#Registers|Registers]].
|-
!style="background-color:#f9f9f9; text-align: left; vertical-align: top;"| ~X
|style="vertical-align: ~X|top;"|1 bit||This 1-bit value is an 'inverted' extension to the ''SIB.index'' field. The inverse of REX.X. See [[#64-bit addressing|64-bit addressing]].
|-
!style="background-color:#f9f9f9; text-align: left; vertical-align: top;"| ~B
|style="vertical-align: ~B|top;"|1 bit||This 1-bit value is an 'inverted' extension to the ''MODRM.rm'' field or the ''SIB.base'' field. The inverse of REX.B. See [[#64-bit addressing|64-bit addressing]].
|-
!style="background-color:#f9f9f9; text-align: left; vertical-align: top;"| map_select
|style="vertical-align: map_select|top;"|5 bits||Specifies the opcode map to use.
|-
!style="background-color:#f9f9f9; text-align: left; vertical-align: top;"| W/E
|style="vertical-align: W/E|top;"|1 bit||For integer instructions: when 1, a 64-bit operand size is used; otherwise, when 0, the default operand size is used (equivalent with REX.W). For non-integer instructions, this bit is a general opcode extension bit.
|-
!style="background-color:#f9f9f9; text-align: left; vertical-align: top;"| ~vvvv
|style="vertical-align: ~vvvv|top;"|4 bits||An additional operand for the instruction. The value of the XMM or YMM register (see [[#Registers|Registers]]) is 'inverted'.
|-
!style="background-color:#f9f9f9; text-align: left; vertical-align: top;"| L
|style="vertical-align: L|top;"|1 bit||When 0, a 128-bit vector lengh is used. Otherwise, when 1, a 256-bit vector length is used.
|-
!style="background-color:#f9f9f9; text-align: left; vertical-align: top;"| pp
|style="vertical-align: pp|top;"|2 bits||Specifies an implied mandatory prefix for the opcode.
{| {{wikitable}}
! Value (binary)
! Implied mandatory prefix
|-
| b0000||none
|-
| b0101||0x66
|-
| b1010||0xF3
|-
| b1111||0xF2
|}
|}
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