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X86-64 Instruction Encoding: Difference between revisions

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X86-64 Instruction Encoding (view source)

Revision as of 14:35, 17 July 2012

780 bytes added ,  11 years ago
→‎64-bit SIB byte: New version
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(→‎64-bit SIB byte: New version)
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<small id="Table6Note1">1: To encode ''disp32'' as in protected/compatibility mode, use the SIB byte.</small>
 
==== 64-bit SIB byte ====
The meaning of the SIB byte whilein using32-bit or 64-bit addressing is as follows. The ModR/M byte's ''MODRM.mod'' field and, the SIB byte's ''SIB.index'' field and ''REX.X''/''VEX.~X''/''XOP.~X'' bitbits (denoted as ''X'') are used vertically, the SIB byte's ''SIB.base'' field and ''REX.B''/''VEX.~B''/''XOP.~B'' bitbits (denoted as ''B'') horizontally. The ''s'' is the [[#SIBScale|scaling factor]].
 
<div style="font-size: 70%">
{| {{wikitable}}
! !! !! !! colspan="8" | REX.B = 0
|-
! Mod
Line 662:
|-
! rowspan="16" | b00 !! 0 !! b000
|[RAX_AX] + ([RAX_AX] * s)||[RCX_CX] + ([RAX_AX] * s)||[RDX_DX] + ([RAX_AX] * s)||[RBX_BX] + ([RAX_AX] * s)||[RSP_SP] + ([RAX_AX] * s)||([RAX_AX] * s) + disp32||[RSI_SI] + ([RAX_AX] * s)||[RDI_DI] + ([RAX_AX] * s)
|-
! 0 !! b001
|[RAX_AX] + ([RCX_CX] * s)||[RCX_CX] + ([RCX_CX] * s)||[RDX_DX] + ([RCX_CX] * s)||[RBX_BX] + ([RCX_CX] * s)||[RSP_SP] + ([RCX_CX] * s)||([RCX_CX] * s) + disp32||[RSI_SI] + ([RCX_CX] * s)||[RDI_DI] + ([RCX_CX] * s)
|-
! 0 !! b010
|[RAX_AX] + ([RDX_DX] * s)||[RCX_CX] + ([RDX_DX] * s)||[RDX_DX] + ([RDX_DX] * s)||[RBX_BX] + ([RDX_DX] * s)||[RSP_SP] + ([RDX_DX] * s)||([RDX_DX] * s) + disp32||[RSI_SI] + ([RDX_DX] * s)||[RDI_DI] + ([RDX_DX] * s)
|-
! 0 !! b011
|[RAX_AX] + ([RBX_BX] * s)||[RCX_CX] + ([RBX_BX] * s)||[RDX_DX] + ([RBX_BX] * s)||[RBX_BX] + ([RBX_BX] * s)||[RSP_SP] + ([RBX_BX] * s)||([RBX_BX] * s) + disp32||[RSI_SI] + ([RBX_BX] * s)||[RDI_DI] + ([RBX_BX] * s)
|-
! 0 !! b100
|[RAX_AX]||[RCX_CX]||[RDX_DX]||[RBX_BX]||[RSP_SP]||disp32||[RSI_SI]||[RDI_DI]
|-
! 0 !! b101
|[RAX_AX] + ([RBP_BP] * s)||[RCX_CX] + ([RBP_BP] * s)||[RDX_DX] + ([RBP_BP] * s)||[RBX_BX] + ([RBP_BP] * s)||[RSP_SP] + ([RBP_BP] * s)||([RBP_BP] * s) + disp32||[RSI_SI] + ([RBP_BP] * s)||[RDI_DI] + ([RBP_BP] * s)
|-
! 0 !! b110
|[RAX_AX] + ([RSI_SI] * s)||[RCX_CX] + ([RSI_SI] * s)||[RDX_DX] + ([RSI_SI] * s)||[RBX_BX] + ([RSI_SI] * s)||[RSP_SP] + ([RSI_SI] * s)||([RSI_SI] * s) + disp32||[RSI_SI] + ([RSI_SI] * s)||[RDI_DI] + ([RSI_SI] * s)
|-
! 0 !! b111
|[RAX_AX] + ([RDI_DI] * s)||[RCX_CX] + ([RDI_DI] * s)||[RDX_DX] + ([RDI_DI] * s)||[RBX_BX] + ([RDI_DI] * s)||[RSP_SP] + ([RDI_DI] * s)||([RDI_DI] * s) + disp32||[RSI_SI] + ([RDI_DI] * s)||[RDI_DI] + ([RDI_DI] * s)
|-
! 1 !! b000
|[RAX_AX] + ([R8R8_] * s)||[RCX_CX] + ([R8R8_] * s)||[RDX_DX] + ([R8R8_] * s)||[RBX_BX] + ([R8R8_] * s)||[RSP_SP] + ([R8R8_] * s)||([R8R8_] * s) + disp32||[RSI_SI] + ([R8R8_] * s)||[RDI_DI] + ([R8R8_] * s)
|-
! 1 !! b001
|[RAX_AX] + ([R9R9_] * s)||[RCX_CX] + ([R9R9_] * s)||[RDX_DX] + ([R9R9_] * s)||[RBX_BX] + ([R9R9_] * s)||[RSP_SP] + ([R9R9_] * s)||([R9R9_] * s) + disp32||[RSI_SI] + ([R9R9_] * s)||[RDI_DI] + ([R9R9_] * s)
|-
! 1 !! b010
|[RAX_AX] + ([R10R10_] * s)||[RCX_CX] + ([R10R10_] * s)||[RDX_DX] + ([R10R10_] * s)||[RBX_BX] + ([R10R10_] * s)||[RSP_SP] + ([R10R10_] * s)||([R10R10_] * s) + disp32||[RSI_SI] + ([R10R10_] * s)||[RDI_DI] + ([R10R10_] * s)
|-
! 1 !! b011
|[RAX_AX] + ([R11R11_] * s)||[RCX_CX] + ([R11R11_] * s)||[RDX_DX] + ([R11R11_] * s)||[RBX_BX] + ([R11R11_] * s)||[RSP_SP] + ([R11R11_] * s)||([R11R11_] * s) + disp32||[RSI_SI] + ([R11R11_] * s)||[RDI_DI] + ([R11R11_] * s)
|-
! 1 !! b100
|[RAX_AX] + ([R12R12_] * s)||[RCX_CX] + ([R12R12_] * s)||[RDX_DX] + ([R12R12_] * s)||[RBX_BX] + ([R12R12_] * s)||[RSP_SP] + ([R12R12_] * s)||disp32||[RSI_SI] + ([R12R12_] * s)||[RDI_DI] + ([R12R12_] * s)
|-
! 1 !! b101
|[RAX_AX] + ([R13R13_] * s)||[RCX_CX] + ([R13R13_] * s)||[RDX_DX] + ([R13R13_] * s)||[RBX_BX] + ([R13R13_] * s)||[RSP_SP] + ([R13R13_] * s)||([R13R13_] * s) + disp32||[RSI_SI] + ([R13R13_] * s)||[RDI_DI] + ([R13R13_] * s)
|-
! 1 !! b110
|[RAX_AX] + ([R14R14_] * s)||[RCX_CX] + ([R14R14_] * s)||[RDX_DX] + ([R14R14_] * s)||[RBX_BX] + ([R14R14_] * s)||[RSP_SP] + ([R14R14_] * s)||([R14R14_] * s) + disp32||[RSI_SI] + ([R14R14_] * s)||[RDI_DI] + ([R14R14_] * s)
|-
! 1 !! b111
|[RAX_AX] + ([R15R15_] * s)||[RCX_CX] + ([R15R15_] * s)||[RDX_DX] + ([R15R15_] * s)||[RBX_BX] + ([R15R15_] * s)||[RSP_SP] + ([R15R15_] * s)||([R15R15_] * s) + disp32||[RSI_SI] + ([R15R15_] * s)||[RDI_DI] + ([R15R15_] * s)
|-
| colspan="11" style="background-color: white; border-top: solid 2px black; border-bottom: solid 2px black; border-left: none; border-right: none;" |
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|-
! rowspan="16" | b00 !! 0 !! b000
|[R8R8_] + ([RAX_AX] * s)||[R9R9_] + ([RAX_AX] * s)||[R10R10_] + ([RAX_AX] * s)||[R11R11_] + ([RAX_AX] * s)||[R12R12_] + ([RAX_AX] * s)||([RAX_AX] * s) + disp32||[R14R14_] + ([RAX_AX] * s)||[R15R15_] + ([RAX_AX] * s)
|-
! 0 !! b001
|[R8R8_] + ([RCX_CX] * s)||[R9R9_] + ([RCX_CX] * s)||[R10R10_] + ([RCX_CX] * s)||[R11R11_] + ([RCX_CX] * s)||[R12R12_] + ([RCX_CX] * s)||([RCX_CX] * s) + disp32||[R14R14_] + ([RCX_CX] * s)||[R15R15_] + ([RCX_CX] * s)
|-
! 0 !! b010
|[R8R8_] + ([RDX_DX] * s)||[R9R9_] + ([RDX_DX] * s)||[R10R10_] + ([RDX_DX] * s)||[R11R11_] + ([RDX_DX] * s)||[R12R12_] + ([RDX_DX] * s)||([RDX_DX] * s) + disp32||[R14R14_] + ([RDX_DX] * s)||[R15R15_] + ([RDX_DX] * s)
|-
! 0 !! b011
|[R8R8_] + ([RBX_BX] * s)||[R9R9_] + ([RBX_BX] * s)||[R10R10_] + ([RBX_BX] * s)||[R11R11_] + ([RBX_BX] * s)||[R12R12_] + ([RBX_BX] * s)||([RBX_BX] * s) + disp32||[R14R14_] + ([RBX_BX] * s)||[R15R15_] + ([RBX_BX] * s)
|-
! 0 !! b100
|[R8R8_]||[R9R9_]||[R10R10_]||[R11R11_]||[R12R12_]||disp32||[R14R14_]||[R15R15_]
|-
! 0 !! b101
|[R8R8_] + ([RBP_BP] * s)||[R9R9_] + ([RBP_BP] * s)||[R10R10_] + ([RBP_BP] * s)||[R11R11_] + ([RBP_BP] * s)||[R12R12_] + ([RBP_BP] * s)||([RBP_BP] * s) + disp32||[R14R14_] + ([RBP_BP] * s)||[R15R15_] + ([RBP_BP] * s)
|-
! 0 !! b110
|[R8R8_] + ([RSI_SI] * s)||[R9R9_] + ([RSI_SI] * s)||[R10R10_] + ([RSI_SI] * s)||[R11R11_] + ([RSI_SI] * s)||[R12R12_] + ([RSI_SI] * s)||([RSI_SI] * s) + disp32||[R14R14_] + ([RSI_SI] * s)||[R15R15_] + ([RSI_SI] * s)
|-
! 0 !! b111
|[R8R8_] + ([RDI_DI] * s)||[R9R9_] + ([RDI_DI] * s)||[R10R10_] + ([RDI_DI] * s)||[R11R11_] + ([RDI_DI] * s)||[R12R12_] + ([RDI_DI] * s)||([RDI_DI] * s) + disp32||[R14R14_] + ([RDI_DI] * s)||[R15R15_] + ([RDI_DI] * s)
|-
! 1 !! b000
|[R8R8_] + ([R8R8_] * s)||[R9R9_] + ([R8R8_] * s)||[R10R10_] + ([R8R8_] * s)||[R11R11_] + ([R8R8_] * s)||[R12R12_] + ([R8R8_] * s)||([R8R8_] * s) + disp32||[R14R14_] + ([R8R8_] * s)||[R15R15_] + ([R8R8_] * s)
|-
! 1 !! b001
|[R8R8_] + ([R9R9_] * s)||[R9R9_] + ([R9R9_] * s)||[R10R10_] + ([R9R9_] * s)||[R11R11_] + ([R9R9_] * s)||[R12R12_] + ([R9R9_] * s)||([R9R9_] * s) + disp32||[R14R14_] + ([R9R9_] * s)||[R15R15_] + ([R9R9_] * s)
|-
! 1 !! b010
|[R8R8_] + ([R10R10_] * s)||[R9R9_] + ([R10R10_] * s)||[R10R10_] + ([R10R10_] * s)||[R11R11_] + ([R10R10_] * s)||[R12R12_] + ([R10R10_] * s)||([R10R10_] * s) + disp32||[R14R14_] + ([R10R10_] * s)||[R15R15_] + ([R10R10_] * s)
|-
! 1 !! b011
|[R8R8_] + ([R11R11_] * s)||[R9R9_] + ([R11R11_] * s)||[R10R10_] + ([R11R11_] * s)||[R11R11_] + ([R11R11_] * s)||[R12R12_] + ([R11R11_] * s)||([R11R11_] * s) + disp32||[R14R14_] + ([R11R11_] * s)||[R15R15_] + ([R11R11_] * s)
|-
! 1 !! b100
|[R8R8_] + ([R12R12_] * s)||[R9R9_] + ([R12R12_] * s)||[R10R10_] + ([R12R12_] * s)||[R11R11_] + ([R12R12_] * s)||[R12R12_] + ([R12R12_] * s)||disp32||[R14R14_] + ([R12R12_] * s)||[R15R15_] + ([R12R12_] * s)
|-
! 1 !! b101
|[R8R8_] + ([R13R13_] * s)||[R9R9_] + ([R13R13_] * s)||[R10R10_] + ([R13R13_] * s)||[R11R11_] + ([R13R13_] * s)||[R12R12_] + ([R13R13_] * s)||([R13R13_] * s) + disp32||[R14R14_] + ([R13R13_] * s)||[R15R15_] + ([R13R13_] * s)
|-
! 1 !! b110
|[R8R8_] + ([R14R14_] * s)||[R9R9_] + ([R14R14_] * s)||[R10R10_] + ([R14R14_] * s)||[R11R11_] + ([R14R14_] * s)||[R12R12_] + ([R14R14_] * s)||([R14R14_] * s) + disp32||[R14R14_] + ([R14R14_] * s)||[R15R15_] + ([R14R14_] * s)
|-
! 1 !! b111
|[R8R8_] + ([R15R15_] * s)||[R9R9_] + ([R15R15_] * s)||[R10R10_] + ([R15R15_] * s)||[R11R11_] + ([R15R15_] * s)||[R12R12_] + ([R15R15_] * s)||([R15R15_] * s) + disp32||[R14R14_] + ([R15R15_] * s)||[R15R15_] + ([R15R15_] * s)
|-
| colspan="11" style="background-color: white; border-top: solid 2px black; border-bottom: solid 2px black; border-left: none; border-right: none;" |
Line 790:
|-
! rowspan="16" | b01 !! 0 !! b000
|[RAX_AX] + ([RAX_AX] * s) + disp8||[RCX_CX] + ([RAX_AX] * s) + disp8||[RDX_DX] + ([RAX_AX] * s) + disp8||[RBX_BX] + ([RAX_AX] * s) + disp8||[RSP_SP] + ([RAX_AX] * s) + disp8||[RBP_BP] + ([RAX_AX] * s) + disp8||[RSI_SI] + ([RAX_AX] * s) + disp8||[RDI_DI] + ([RAX_AX] * s) + disp8
|-
! 0 !! b001
|[RAX_AX] + ([RCX_CX] * s) + disp8||[RCX_CX] + ([RCX_CX] * s) + disp8||[RDX_DX] + ([RCX_CX] * s) + disp8||[RBX_BX] + ([RCX_CX] * s) + disp8||[RSP_SP] + ([RCX_CX] * s) + disp8||[RBP_BP] + ([RCX_CX] * s) + disp8||[RSI_SI] + ([RCX_CX] * s) + disp8||[RDI_DI] + ([RCX_CX] * s) + disp8
|-
! 0 !! b010
|[RAX_AX] + ([RDX_DX] * s) + disp8||[RCX_CX] + ([RDX_DX] * s) + disp8||[RDX_DX] + ([RDX_DX] * s) + disp8||[RBX_BX] + ([RDX_DX] * s) + disp8||[RSP_SP] + ([RDX_DX] * s) + disp8||[RBP_BP] + ([RDX_DX] * s) + disp8||[RSI_SI] + ([RDX_DX] * s) + disp8||[RDI_DI] + ([RDX_DX] * s) + disp8
|-
! 0 !! b011
|[RAX_AX] + ([RBX_BX] * s) + disp8||[RCX_CX] + ([RBX_BX] * s) + disp8||[RDX_DX] + ([RBX_BX] * s) + disp8||[RBX_BX] + ([RBX_BX] * s) + disp8||[RSP_SP] + ([RBX_BX] * s) + disp8||[RBP_BP] + ([RBX_BX] * s) + disp8||[RSI_SI] + ([RBX_BX] * s) + disp8||[RDI_DI] + ([RBX_BX] * s) + disp8
|-
! 0 !! b100
|[RAX_AX] + disp8||[RCX_CX] + disp8||[RDX_DX] + disp8||[RBX_BX] + disp8||[RSP_SP] + disp8||[RBP_BP] + disp8||[RSI_SI] + disp8||[RDI_DI] + disp8
|-
! 0 !! b101
|[RAX_AX] + ([RBP_BP] * s) + disp8||[RCX_CX] + ([RBP_BP] * s) + disp8||[RDX_DX] + ([RBP_BP] * s) + disp8||[RBX_BX] + ([RBP_BP] * s) + disp8||[RSP_SP] + ([RBP_BP] * s) + disp8||[RBP_BP] + ([RBP_BP] * s) + disp8||[RSI_SI] + ([RBP_BP] * s) + disp8||[RDI_DI] + ([RBP_BP] * s) + disp8
|-
! 0 !! b110
|[RAX_AX] + ([RSI_SI] * s) + disp8||[RCX_CX] + ([RSI_SI] * s) + disp8||[RDX_DX] + ([RSI_SI] * s) + disp8||[RBX_BX] + ([RSI_SI] * s) + disp8||[RSP_SP] + ([RSI_SI] * s) + disp8||[RBP_BP] + ([RSI_SI] * s) + disp8||[RSI_SI] + ([RSI_SI] * s) + disp8||[RDI_DI] + ([RSI_SI] * s) + disp8
|-
! 0 !! b111
|[RAX_AX] + ([RDI_DI] * s) + disp8||[RCX_CX] + ([RDI_DI] * s) + disp8||[RDX_DX] + ([RDI_DI] * s) + disp8||[RBX_BX] + ([RDI_DI] * s) + disp8||[RSP_SP] + ([RDI_DI] * s) + disp8||[RBP_BP] + ([RDI_DI] * s) + disp8||[RSI_SI] + ([RDI_DI] * s) + disp8||[RDI_DI] + ([RDI_DI] * s) + disp8
|-
! 1 !! b000
|[RAX_AX] + ([R8R8_] * s) + disp8||[RCX_CX] + ([R8R8_] * s) + disp8||[RDX_DX] + ([R8R8_] * s) + disp8||[RBX_BX] + ([R8R8_] * s) + disp8||[RSP_SP] + ([R8R8_] * s) + disp8||[RBP_BP] + ([R8R8_] * s) + disp8||[RSI_SI] + ([R8R8_] * s) + disp8||[RDI_DI] + ([R8R8_] * s) + disp8
|-
! 1 !! b001
|[RAX_AX] + ([R9R9_] * s) + disp8||[RCX_CX] + ([R9R9_] * s) + disp8||[RDX_DX] + ([R9R9_] * s) + disp8||[RBX_BX] + ([R9R9_] * s) + disp8||[RSP_SP] + ([R9R9_] * s) + disp8||[RBP_BP] + ([R9R9_] * s) + disp8||[RSI_SI] + ([R9R9_] * s) + disp8||[RDI_DI] + ([R9R9_] * s) + disp8
|-
! 1 !! b010
|[RAX_AX] + ([R10R10_] * s) + disp8||[RCX_CX] + ([R10R10_] * s) + disp8||[RDX_DX] + ([R10R10_] * s) + disp8||[RBX_BX] + ([R10R10_] * s) + disp8||[RSP_SP] + ([R10R10_] * s) + disp8||[RBP_BP] + ([R10R10_] * s) + disp8||[RSI_SI] + ([R10R10_] * s) + disp8||[RDI_DI] + ([R10R10_] * s) + disp8
|-
! 1 !! b011
|[RAX_AX] + ([R11R11_] * s) + disp8||[RCX_CX] + ([R11R11_] * s) + disp8||[RDX_DX] + ([R11R11_] * s) + disp8||[RBX_BX] + ([R11R11_] * s) + disp8||[RSP_SP] + ([R11R11_] * s) + disp8||[RBP_BP] + ([R11R11_] * s) + disp8||[RSI_SI] + ([R11R11_] * s) + disp8||[RDI_DI] + ([R11R11_] * s) + disp8
|-
! 1 !! b100
|[RAX_AX] + ([R12R12_] * s) + disp8||[RCX_CX] + ([R12R12_] * s) + disp8||[RDX_DX] + ([R12R12_] * s) + disp8||[RBX_BX] + ([R12R12_] * s) + disp8||[RSP_SP] + ([R12R12_] * s) + disp8||[RBP_BP] + ([R12R12_] * s) + disp8||[RSI_SI] + ([R12R12_] * s) + disp8||[RDI_DI] + ([R12R12_] * s) + disp8
|-
! 1 !! b101
|[RAX_AX] + ([R13R13_] * s) + disp8||[RCX_CX] + ([R13R13_] * s) + disp8||[RDX_DX] + ([R13R13_] * s) + disp8||[RBX_BX] + ([R13R13_] * s) + disp8||[RSP_SP] + ([R13R13_] * s) + disp8||[RBP_BP] + ([R13R13_] * s) + disp8||[RSI_SI] + ([R13R13_] * s) + disp8||[RDI_DI] + ([R13R13_] * s) + disp8
|-
! 1 !! b110
|[RAX_AX] + ([R14R14_] * s) + disp8||[RCX_CX] + ([R14R14_] * s) + disp8||[RDX_DX] + ([R14R14_] * s) + disp8||[RBX_BX] + ([R14R14_] * s) + disp8||[RSP_SP] + ([R14R14_] * s) + disp8||[RBP_BP] + ([R14R14_] * s) + disp8||[RSI_SI] + ([R14R14_] * s) + disp8||[RDI_DI] + ([R14R14_] * s) + disp8
|-
! 1 !! b111
|[RAX_AX] + ([R15R15_] * s) + disp8||[RCX_CX] + ([R15R15_] * s) + disp8||[RDX_DX] + ([R15R15_] * s) + disp8||[RBX_BX] + ([R15R15_] * s) + disp8||[RSP_SP] + ([R15R15_] * s) + disp8||[RBP_BP] + ([R15R15_] * s) + disp8||[RSI_SI] + ([R15R15_] * s) + disp8||[RDI_DI] + ([R15R15_] * s) + disp8
|-
| colspan="11" style="background-color: white; border-top: solid 2px black; border-bottom: solid 2px black; border-left: none; border-right: none;" |
Line 854:
|-
! rowspan="16" | b01 !! 0 !! b000
|[R8R8_] + ([RAX_AX] * s) + disp8||[R9R9_] + ([RAX_AX] * s) + disp8||[R10R10_] + ([RAX_AX] * s) + disp8||[R11R11_] + ([RAX_AX] * s) + disp8||[R12R12_] + ([RAX_AX] * s) + disp8||[R13R13_] + ([RAX_AX] * s) + disp8||[R14R14_] + ([RAX_AX] * s) + disp8||[R15R15_] + ([RAX_AX] * s) + disp8
|-
! 0 !! b001
|[R8R8_] + ([RCX_CX] * s) + disp8||[R9R9_] + ([RCX_CX] * s) + disp8||[R10R10_] + ([RCX_CX] * s) + disp8||[R11R11_] + ([RCX_CX] * s) + disp8||[R12R12_] + ([RCX_CX] * s) + disp8||[R13R13_] + ([RCX_CX] * s) + disp8||[R14R14_] + ([RCX_CX] * s) + disp8||[R15R15_] + ([RCX_CX] * s) + disp8
|-
! 0 !! b010
|[R8R8_] + ([RDX_DX] * s) + disp8||[R9R9_] + ([RDX_DX] * s) + disp8||[R10R10_] + ([RDX_DX] * s) + disp8||[R11R11_] + ([RDX_DX] * s) + disp8||[R12R12_] + ([RDX_DX] * s) + disp8||[R13R13_] + ([RDX_DX] * s) + disp8||[R14R14_] + ([RDX_DX] * s) + disp8||[R15R15_] + ([RDX_DX] * s) + disp8
|-
! 0 !! b011
|[R8R8_] + ([RBX_BX] * s) + disp8||[R9R9_] + ([RBX_BX] * s) + disp8||[R10R10_] + ([RBX_BX] * s) + disp8||[R11R11_] + ([RBX_BX] * s) + disp8||[R12R12_] + ([RBX_BX] * s) + disp8||[R13R13_] + ([RBX_BX] * s) + disp8||[R14R14_] + ([RBX_BX] * s) + disp8||[R15R15_] + ([RBX_BX] * s) + disp8
|-
! 0 !! b100
|[R8R8_] + disp8||[R9R9_] + disp8||[R10R10_] + disp8||[R11R11_] + disp8||[R12R12_] + disp8||[R13R13_] + disp8||[R14R14_] + disp8||[R15R15_] + disp8
|-
! 0 !! b101
|[R8R8_] + ([RBP_BP] * s) + disp8||[R9R9_] + ([RBP_BP] * s) + disp8||[R10R10_] + ([RBP_BP] * s) + disp8||[R11R11_] + ([RBP_BP] * s) + disp8||[R12R12_] + ([RBP_BP] * s) + disp8||[R13R13_] + ([RBP_BP] * s) + disp8||[R14R14_] + ([RBP_BP] * s) + disp8||[R15R15_] + ([RBP_BP] * s) + disp8
|-
! 0 !! b110
|[R8R8_] + ([RSI_SI] * s) + disp8||[R9R9_] + ([RSI_SI] * s) + disp8||[R10R10_] + ([RSI_SI] * s) + disp8||[R11R11_] + ([RSI_SI] * s) + disp8||[R12R12_] + ([RSI_SI] * s) + disp8||[R13R13_] + ([RSI_SI] * s) + disp8||[R14R14_] + ([RSI_SI] * s) + disp8||[R15R15_] + ([RSI_SI] * s) + disp8
|-
! 0 !! b111
|[R8R8_] + ([RDI_DI] * s) + disp8||[R9R9_] + ([RDI_DI] * s) + disp8||[R10R10_] + ([RDI_DI] * s) + disp8||[R11R11_] + ([RDI_DI] * s) + disp8||[R12R12_] + ([RDI_DI] * s) + disp8||[R13R13_] + ([RDI_DI] * s) + disp8||[R14R14_] + ([RDI_DI] * s) + disp8||[R15R15_] + ([RDI_DI] * s) + disp8
|-
! 1 !! b000
|[R8R8_] + ([R8R8_] * s) + disp8||[R9R9_] + ([R8R8_] * s) + disp8||[R10R10_] + ([R8R8_] * s) + disp8||[R11R11_] + ([R8R8_] * s) + disp8||[R12R12_] + ([R8R8_] * s) + disp8||[R13R13_] + ([R8R8_] * s) + disp8||[R14R14_] + ([R8R8_] * s) + disp8||[R15R15_] + ([R8R8_] * s) + disp8
|-
! 1 !! b001
|[R8R8_] + ([R9R9_] * s) + disp8||[R9R9_] + ([R9R9_] * s) + disp8||[R10R10_] + ([R9R9_] * s) + disp8||[R11R11_] + ([R9R9_] * s) + disp8||[R12R12_] + ([R9R9_] * s) + disp8||[R13R13_] + ([R9R9_] * s) + disp8||[R14R14_] + ([R9R9_] * s) + disp8||[R15R15_] + ([R9R9_] * s) + disp8
|-
! 1 !! b010
|[R8R8_] + ([R10R10_] * s) + disp8||[R9R9_] + ([R10R10_] * s) + disp8||[R10R10_] + ([R10R10_] * s) + disp8||[R11R11_] + ([R10R10_] * s) + disp8||[R12R12_] + ([R10R10_] * s) + disp8||[R13R13_] + ([R10R10_] * s) + disp8||[R14R14_] + ([R10R10_] * s) + disp8||[R15R15_] + ([R10R10_] * s) + disp8
|-
! 1 !! b011
|[R8R8_] + ([R11R11_] * s) + disp8||[R9R9_] + ([R11R11_] * s) + disp8||[R10R10_] + ([R11R11_] * s) + disp8||[R11R11_] + ([R11R11_] * s) + disp8||[R12R12_] + ([R11R11_] * s) + disp8||[R13R13_] + ([R11R11_] * s) + disp8||[R14R14_] + ([R11R11_] * s) + disp8||[R15R15_] + ([R11R11_] * s) + disp8
|-
! 1 !! b100
|[R8R8_] + ([R12R12_] * s) + disp8||[R9R9_] + ([R12R12_] * s) + disp8||[R10R10_] + ([R12R12_] * s) + disp8||[R11R11_] + ([R12R12_] * s) + disp8||[R12R12_] + ([R12R12_] * s) + disp8||[R13R13_] + ([R12R12_] * s) + disp8||[R14R14_] + ([R12R12_] * s) + disp8||[R15R15_] + ([R12R12_] * s) + disp8
|-
! 1 !! b101
|[R8R8_] + ([R13R13_] * s) + disp8||[R9R9_] + ([R13R13_] * s) + disp8||[R10R10_] + ([R13R13_] * s) + disp8||[R11R11_] + ([R13R13_] * s) + disp8||[R12R12_] + ([R13R13_] * s) + disp8||[R13R13_] + ([R13R13_] * s) + disp8||[R14R14_] + ([R13R13_] * s) + disp8||[R15R15_] + ([R13R13_] * s) + disp8
|-
! 1 !! b110
|[R8R8_] + ([R14R14_] * s) + disp8||[R9R9_] + ([R14R14_] * s) + disp8||[R10R10_] + ([R14R14_] * s) + disp8||[R11R11_] + ([R14R14_] * s) + disp8||[R12R12_] + ([R14R14_] * s) + disp8||[R13R13_] + ([R14R14_] * s) + disp8||[R14R14_] + ([R14R14_] * s) + disp8||[R15R15_] + ([R14R14_] * s) + disp8
|-
! 1 !! b111
|[R8R8_] + ([R15R15_] * s) + disp8||[R9R9_] + ([R15R15_] * s) + disp8||[R10R10_] + ([R15R15_] * s) + disp8||[R11R11_] + ([R15R15_] * s) + disp8||[R12R12_] + ([R15R15_] * s) + disp8||[R13R13_] + ([R15R15_] * s) + disp8||[R14R14_] + ([R15R15_] * s) + disp8||[R15R15_] + ([R15R15_] * s) + disp8
|-
| colspan="11" style="background-color: white; border-top: solid 2px black; border-bottom: solid 2px black; border-left: none; border-right: none;" |
Line 918:
|-
! rowspan="16" | b10 !! 0 !! b000
|[RAX_AX] + ([RAX_AX] * s) + disp32||[RCX_CX] + ([RAX_AX] * s) + disp32||[RDX_DX] + ([RAX_AX] * s) + disp32||[RBX_BX] + ([RAX_AX] * s) + disp32||[RSP_SP] + ([RAX_AX] * s) + disp32||[RBP_BP] + ([RAX_AX] * s) + disp32||[RSI_SI] + ([RAX_AX] * s) + disp32||[RDI_DI] + ([RAX_AX] * s) + disp32
|-
! 0 !! b001
|[RAX_AX] + ([RCX_CX] * s) + disp32||[RCX_CX] + ([RCX_CX] * s) + disp32||[RDX_DX] + ([RCX_CX] * s) + disp32||[RBX_BX] + ([RCX_CX] * s) + disp32||[RSP_SP] + ([RCX_CX] * s) + disp32||[RBP_BP] + ([RCX_CX] * s) + disp32||[RSI_SI] + ([RCX_CX] * s) + disp32||[RDI_DI] + ([RCX_CX] * s) + disp32
|-
! 0 !! b010
|[RAX_AX] + ([RDX_DX] * s) + disp32||[RCX_CX] + ([RDX_DX] * s) + disp32||[RDX_DX] + ([RDX_DX] * s) + disp32||[RBX_BX] + ([RDX_DX] * s) + disp32||[RSP_SP] + ([RDX_DX] * s) + disp32||[RBP_BP] + ([RDX_DX] * s) + disp32||[RSI_SI] + ([RDX_DX] * s) + disp32||[RDI_DI] + ([RDX_DX] * s) + disp32
|-
! 0 !! b011
|[RAX_AX] + ([RBX_BX] * s) + disp32||[RCX_CX] + ([RBX_BX] * s) + disp32||[RDX_DX] + ([RBX_BX] * s) + disp32||[RBX_BX] + ([RBX_BX] * s) + disp32||[RSP_SP] + ([RBX_BX] * s) + disp32||[RBP_BP] + ([RBX_BX] * s) + disp32||[RSI_SI] + ([RBX_BX] * s) + disp32||[RDI_DI] + ([RBX_BX] * s) + disp32
|-
! 0 !! b100
|[RAX_AX] + disp32||[RCX_CX] + disp32||[RDX_DX] + disp32||[RBX_BX] + disp32||[RSP_SP] + disp32||[RBP_BP] + disp32||[RSI_SI] + disp32||[RDI_DI] + disp32
|-
! 0 !! b101
|[RAX_AX] + ([RBP_BP] * s) + disp32||[RCX_CX] + ([RBP_BP] * s) + disp32||[RDX_DX] + ([RBP_BP] * s) + disp32||[RBX_BX] + ([RBP_BP] * s) + disp32||[RSP_SP] + ([RBP_BP] * s) + disp32||[RBP_BP] + ([RBP_BP] * s) + disp32||[RSI_SI] + ([RBP_BP] * s) + disp32||[RDI_DI] + ([RBP_BP] * s) + disp32
|-
! 0 !! b110
|[RAX_AX] + ([RSI_SI] * s) + disp32||[RCX_CX] + ([RSI_SI] * s) + disp32||[RDX_DX] + ([RSI_SI] * s) + disp32||[RBX_BX] + ([RSI_SI] * s) + disp32||[RSP_SP] + ([RSI_SI] * s) + disp32||[RBP_BP] + ([RSI_SI] * s) + disp32||[RSI_SI] + ([RSI_SI] * s) + disp32||[RDI_DI] + ([RSI_SI] * s) + disp32
|-
! 0 !! b111
|[RAX_AX] + ([RDI_DI] * s) + disp32||[RCX_CX] + ([RDI_DI] * s) + disp32||[RDX_DX] + ([RDI_DI] * s) + disp32||[RBX_BX] + ([RDI_DI] * s) + disp32||[RSP_SP] + ([RDI_DI] * s) + disp32||[RBP_BP] + ([RDI_DI] * s) + disp32||[RSI_SI] + ([RDI_DI] * s) + disp32||[RDI_DI] + ([RDI_DI] * s) + disp32
|-
! 1 !! b000
|[RAX_AX] + ([R8R8_] * s) + disp32||[RCX_CX] + ([R8R8_] * s) + disp32||[RDX_DX] + ([R8R8_] * s) + disp32||[RBX_BX] + ([R8R8_] * s) + disp32||[RSP_SP] + ([R8R8_] * s) + disp32||[RBP_BP] + ([R8R8_] * s) + disp32||[RSI_SI] + ([R8R8_] * s) + disp32||[RDI_DI] + ([R8R8_] * s) + disp32
|-
! 1 !! b001
|[RAX_AX] + ([R9R9_] * s) + disp32||[RCX_CX] + ([R9R9_] * s) + disp32||[RDX_DX] + ([R9R9_] * s) + disp32||[RBX_BX] + ([R9R9_] * s) + disp32||[RSP_SP] + ([R9R9_] * s) + disp32||[RBP_BP] + ([R9R9_] * s) + disp32||[RSI_SI] + ([R9R9_] * s) + disp32||[RDI_DI] + ([R9R9_] * s) + disp32
|-
! 1 !! b010
|[RAX_AX] + ([R10R10_] * s) + disp32||[RCX_CX] + ([R10R10_] * s) + disp32||[RDX_DX] + ([R10R10_] * s) + disp32||[RBX_BX] + ([R10R10_] * s) + disp32||[RSP_SP] + ([R10R10_] * s) + disp32||[RBP_BP] + ([R10R10_] * s) + disp32||[RSI_SI] + ([R10R10_] * s) + disp32||[RDI_DI] + ([R10R10_] * s) + disp32
|-
! 1 !! b011
|[RAX_AX] + ([R11R11_] * s) + disp32||[RCX_CX] + ([R11R11_] * s) + disp32||[RDX_DX] + ([R11R11_] * s) + disp32||[RBX_BX] + ([R11R11_] * s) + disp32||[RSP_SP] + ([R11R11_] * s) + disp32||[RBP_BP] + ([R11R11_] * s) + disp32||[RSI_SI] + ([R11R11_] * s) + disp32||[RDI_DI] + ([R11R11_] * s) + disp32
|-
! 1 !! b100
|[RAX_AX] + ([R12R12_] * s) + disp32||[RCX_CX] + ([R12R12_] * s) + disp32||[RDX_DX] + ([R12R12_] * s) + disp32||[RBX_BX] + ([R12R12_] * s) + disp32||[RSP_SP] + ([R12R12_] * s) + disp32||[RBP_BP] + ([R12R12_] * s) + disp32||[RSI_SI] + ([R12R12_] * s) + disp32||[RDI_DI] + ([R12R12_] * s) + disp32
|-
! 1 !! b101
|[RAX_AX] + ([R13R13_] * s) + disp32||[RCX_CX] + ([R13R13_] * s) + disp32||[RDX_DX] + ([R13R13_] * s) + disp32||[RBX_BX] + ([R13R13_] * s) + disp32||[RSP_SP] + ([R13R13_] * s) + disp32||[RBP_BP] + ([R13R13_] * s) + disp32||[RSI_SI] + ([R13R13_] * s) + disp32||[RDI_DI] + ([R13R13_] * s) + disp32
|-
! 1 !! b110
|[RAX_AX] + ([R14R14_] * s) + disp32||[RCX_CX] + ([R14R14_] * s) + disp32||[RDX_DX] + ([R14R14_] * s) + disp32||[RBX_BX] + ([R14R14_] * s) + disp32||[RSP_SP] + ([R14R14_] * s) + disp32||[RBP_BP] + ([R14R14_] * s) + disp32||[RSI_SI] + ([R14R14_] * s) + disp32||[RDI_DI] + ([R14R14_] * s) + disp32
|-
! 1 !! b111
|[RAX_AX] + ([R15R15_] * s) + disp32||[RCX_CX] + ([R15R15_] * s) + disp32||[RDX_DX] + ([R15R15_] * s) + disp32||[RBX_BX] + ([R15R15_] * s) + disp32||[RSP_SP] + ([R15R15_] * s) + disp32||[RBP_BP] + ([R15R15_] * s) + disp32||[RSI_SI] + ([R15R15_] * s) + disp32||[RDI_DI] + ([R15R15_] * s) + disp32
|-
| colspan="11" style="background-color: white; border-top: solid 2px black; border-bottom: solid 2px black; border-left: none; border-right: none;" |
Line 982:
|-
! rowspan="16" | b10 !! 0 !! b000
|[R8R8_] + ([RAX_AX] * s) + disp32||[R9R9_] + ([RAX_AX] * s) + disp32||[R10R10_] + ([RAX_AX] * s) + disp32||[R11R11_] + ([RAX_AX] * s) + disp32||[R12R12_] + ([RAX_AX] * s) + disp32||[R13R13_] + ([RAX_AX] * s) + disp32||[R14R14_] + ([RAX_AX] * s) + disp32||[R15R15_] + ([RAX_AX] * s) + disp32
|-
! 0 !! b001
|[R8R8_] + ([RCX_CX] * s) + disp32||[R9R9_] + ([RCX_CX] * s) + disp32||[R10R10_] + ([RCX_CX] * s) + disp32||[R11R11_] + ([RCX_CX] * s) + disp32||[R12R12_] + ([RCX_CX] * s) + disp32||[R13R13_] + ([RCX_CX] * s) + disp32||[R14R14_] + ([RCX_CX] * s) + disp32||[R15R15_] + ([RCX_CX] * s) + disp32
|-
! 0 !! b010
|[R8R8_] + ([RDX_DX] * s) + disp32||[R9R9_] + ([RDX_DX] * s) + disp32||[R10R10_] + ([RDX_DX] * s) + disp32||[R11R11_] + ([RDX_DX] * s) + disp32||[R12R12_] + ([RDX_DX] * s) + disp32||[R13R13_] + ([RDX_DX] * s) + disp32||[R14R14_] + ([RDX_DX] * s) + disp32||[R15R15_] + ([RDX_DX] * s) + disp32
|-
! 0 !! b011
|[R8R8_] + ([RBX_BX] * s) + disp32||[R9R9_] + ([RBX_BX] * s) + disp32||[R10R10_] + ([RBX_BX] * s) + disp32||[R11R11_] + ([RBX_BX] * s) + disp32||[R12R12_] + ([RBX_BX] * s) + disp32||[R13R13_] + ([RBX_BX] * s) + disp32||[R14R14_] + ([RBX_BX] * s) + disp32||[R15R15_] + ([RBX_BX] * s) + disp32
|-
! 0 !! b100
|[R8R8_] + disp32||[R9R9_] + disp32||[R10R10_] + disp32||[R11R11_] + disp32||[R12R12_] + disp32||[R13R13_] + disp32||[R14R14_] + disp32||[R15R15_] + disp32
|-
! 0 !! b101
|[R8R8_] + ([RBP_BP] * s) + disp32||[R9R9_] + ([RBP_BP] * s) + disp32||[R10R10_] + ([RBP_BP] * s) + disp32||[R11R11_] + ([RBP_BP] * s) + disp32||[R12R12_] + ([RBP_BP] * s) + disp32||[R13R13_] + ([RBP_BP] * s) + disp32||[R14R14_] + ([RBP_BP] * s) + disp32||[R15R15_] + ([RBP_BP] * s) + disp32
|-
! 0 !! b110
|[R8R8_] + ([RSI_SI] * s) + disp32||[R9R9_] + ([RSI_SI] * s) + disp32||[R10R10_] + ([RSI_SI] * s) + disp32||[R11R11_] + ([RSI_SI] * s) + disp32||[R12R12_] + ([RSI_SI] * s) + disp32||[R13R13_] + ([RSI_SI] * s) + disp32||[R14R14_] + ([RSI_SI] * s) + disp32||[R15R15_] + ([RSI_SI] * s) + disp32
|-
! 0 !! b111
|[R8R8_] + ([RDI_DI] * s) + disp32||[R9R9_] + ([RDI_DI] * s) + disp32||[R10R10_] + ([RDI_DI] * s) + disp32||[R11R11_] + ([RDI_DI] * s) + disp32||[R12R12_] + ([RDI_DI] * s) + disp32||[R13R13_] + ([RDI_DI] * s) + disp32||[R14R14_] + ([RDI_DI] * s) + disp32||[R15R15_] + ([RDI_DI] * s) + disp32
|-
! 1 !! b000
|[R8R8_] + ([R8R8_] * s) + disp32||[R9R9_] + ([R8R8_] * s) + disp32||[R10R10_] + ([R8R8_] * s) + disp32||[R11R11_] + ([R8R8_] * s) + disp32||[R12R12_] + ([R8R8_] * s) + disp32||[R13R13_] + ([R8R8_] * s) + disp32||[R14R14_] + ([R8R8_] * s) + disp32||[R15R15_] + ([R8R8_] * s) + disp32
|-
! 1 !! b001
|[R8R8_] + ([R9R9_] * s) + disp32||[R9R9_] + ([R9R9_] * s) + disp32||[R10R10_] + ([R9R9_] * s) + disp32||[R11R11_] + ([R9R9_] * s) + disp32||[R12R12_] + ([R9R9_] * s) + disp32||[R13R13_] + ([R9R9_] * s) + disp32||[R14R14_] + ([R9R9_] * s) + disp32||[R15R15_] + ([R9R9_] * s) + disp32
|-
! 1 !! b010
|[R8R8_] + ([R10R10_] * s) + disp32||[R9R9_] + ([R10R10_] * s) + disp32||[R10R10_] + ([R10R10_] * s) + disp32||[R11R11_] + ([R10R10_] * s) + disp32||[R12R12_] + ([R10R10_] * s) + disp32||[R13R13_] + ([R10R10_] * s) + disp32||[R14R14_] + ([R10R10_] * s) + disp32||[R15R15_] + ([R10R10_] * s) + disp32
|-
! 1 !! b011
|[R8R8_] + ([R11R11_] * s) + disp32||[R9R9_] + ([R11R11_] * s) + disp32||[R10R10_] + ([R11R11_] * s) + disp32||[R11R11_] + ([R11R11_] * s) + disp32||[R12R12_] + ([R11R11_] * s) + disp32||[R13R13_] + ([R11R11_] * s) + disp32||[R14R14_] + ([R11R11_] * s) + disp32||[R15R15_] + ([R11R11_] * s) + disp32
|-
! 1 !! b100
|[R8R8_] + ([R12R12_] * s) + disp32||[R9R9_] + ([R12R12_] * s) + disp32||[R10R10_] + ([R12R12_] * s) + disp32||[R11R11_] + ([R12R12_] * s) + disp32||[R12R12_] + ([R12R12_] * s) + disp32||[R13R13_] + ([R12R12_] * s) + disp32||[R14R14_] + ([R12R12_] * s) + disp32||[R15R15_] + ([R12R12_] * s) + disp32
|-
! 1 !! b101
|[R8R8_] + ([R13R13_] * s) + disp32||[R9R9_] + ([R13R13_] * s) + disp32||[R10R10_] + ([R13R13_] * s) + disp32||[R11R11_] + ([R13R13_] * s) + disp32||[R12R12_] + ([R13R13_] * s) + disp32||[R13R13_] + ([R13R13_] * s) + disp32||[R14R14_] + ([R13R13_] * s) + disp32||[R15R15_] + ([R13R13_] * s) + disp32
|-
! 1 !! b110
|[R8R8_] + ([R14R14_] * s) + disp32||[R9R9_] + ([R14R14_] * s) + disp32||[R10R10_] + ([R14R14_] * s) + disp32||[R11R11_] + ([R14R14_] * s) + disp32||[R12R12_] + ([R14R14_] * s) + disp32||[R13R13_] + ([R14R14_] * s) + disp32||[R14R14_] + ([R14R14_] * s) + disp32||[R15R15_] + ([R14R14_] * s) + disp32
|-
! 1 !! b111
|[R8R8_] + ([R15R15_] * s) + disp32||[R9R9_] + ([R15R15_] * s) + disp32||[R10R10_] + ([R15R15_] * s) + disp32||[R11R11_] + ([R15R15_] * s) + disp32||[R12R12_] + ([R15R15_] * s) + disp32||[R13R13_] + ([R15R15_] * s) + disp32||[R14R14_] + ([R15R15_] * s) + disp32||[R15R15_] + ([R15R15_] * s) + disp32
|}
</div>
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