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== Registers ==
The registers are encoded using the 4-bit values in the X.Reg column of the following table. ''X.Reg'' is in binary.
<div style="font-size: smaller">
{| {{wikitable}}
{| {{wikitable|background: white;}}
! X.Reg!! 8-bit GP!! 16-bit GP!! 32-bit GP!! 64-bit GP!! 64-bit MMX!! 128-bit XMM!! 256-bit YMM!! 16-bit Segment!! 32-bit Control!! 32-bit Debug
!style="background-color: #f9f9f9"| X.Reg
!style="background-color: #f9f9f9"| 8-bit GP
!style="background-color: #f9f9f9"| 16-bit GP
!style="background-color: #f9f9f9"| 32-bit GP
!style="background-color: #f9f9f9"| 64-bit GP
!style="background-color: #f9f9f9"| 80-bit x87
!style="background-color: #f9f9f9"| 64-bit MMX
!style="background-color: #f9f9f9"| 128-bit XMM
!style="background-color: #f9f9f9"| 256-bit YMM
!style="background-color: #f9f9f9"| 16-bit Segment
!style="background-color: #f9f9f9"| 32-bit Control
!style="background-color: #f9f9f9"| 32-bit Debug
|-
!style="background-color: #f9f9f9"| 0.000 (0)
| b0.000 (0)||AL||AX||EAX||RAX||MM0||XMM0||YMM0||ES||CR0||DR0
|AL||AX||EAX||RAX||ST0||MMX0||XMM0||YMM0||ES||CR0||DR0
|-
!style="background-color: #f9f9f9"| 0.001 (1)
| b0.001 (1)||CL||CX||ECX||RCX||MM1||XMM1||YMM1||CS||CR1||DR1
|CL||CX||ECX||RCX||ST1||MMX1||XMM1||YMM1||CS||CR1||DR1
|-
!style="background-color: #f9f9f9"| 0.010 (2)
| b0.010 (2)||DL||DX||EDX||RDX||MM2||XMM2||YMM2||SS||CR2||DR2
|DL||DX||EDX||RDX||ST2||MMX2||XMM2||YMM2||SS||CR2||DR2
|-
!style="background-color: #f9f9f9"| 0.011 (3)
| b0.011 (3)||BL||BX||EBX||RBX||MM3||XMM3||YMM3||DS||CR3||DR3
|BL||BX||EBX||RBX||ST3||MMX3||XMM3||YMM3||DS||CR3||DR3
|-
!style="background-color: #f9f9f9"| 0.100 (4)
| b0.100 (4)||AH, SPL<span style="vertical-align: super">[[#Table1Note1|1]]</span>||SP||ESP||RSP||MM4||XMM4||YMM4||FS||CR4||DR4
|AH, SPL<span style="vertical-align: super">[[#Table1Note1|1]]</span>||SP||ESP||RSP||ST4||MMX4||XMM4||YMM4||FS||CR4||DR4
|-
!style="background-color: #f9f9f9"| 0.101 (5)
| b0.101 (5)||CH, BPL<span style="vertical-align: super">[[#Table1Note1|1]]</span>||BP||EBP||RBP||MM5||XMM5||YMM5||GS||CR5||DR5
|CH, BPL<span style="vertical-align: super">[[#Table1Note1|1]]</span>||BP||EBP||RBP||ST5||MMX5||XMM5||YMM5||GS||CR5||DR5
|-
!style="background-color: #f9f9f9"| 0.110 (6)
| b0.110 (6)||DH, SIL<span style="vertical-align: super">[[#Table1Note1|1]]</span>||SI||ESI||RSI||MM6||XMM6||YMM6||invalid||CR6||DR6
|DH, SIL<span style="vertical-align: super">[[#Table1Note1|1]]</span>||SI||ESI||RSI||ST6||MMX6||XMM6||YMM6||-||CR6||DR6
|-
!style="background-color: #f9f9f9"| 0.111 (7)
| b0.111 (7)||BH, DIL<span style="vertical-align: super">[[#Table1Note1|1]]</span>||DI||EDI||RDI||MM7||XMM7||YMM7||invalid||CR7||DR7
|BH, DIL<span style="vertical-align: super">[[#Table1Note1|1]]</span>||DI||EDI||RDI||ST7||MMX7||XMM7||YMM7||-||CR7||DR7
|-
!style="background-color: #f9f9f9"| 1.000 (8)
| b1.000 (8)||R8L||R8W||R8D||R8||MM0||XMM8||YMM8||ES||CR8||DR8
|R8L||R8W||R8D||R8||-||MMX0||XMM8||YMM8||ES||CR8||DR8
|-
!style="background-color: #f9f9f9"| 1.001 (9)
| b1.001 (9)||R9L||R9W||R9D||R9||MM1||XMM9||YMM9||CS||CR9||DR9
|R9L||R9W||R9D||R9||-||MMX1||XMM9||YMM9||CS||CR9||DR9
|-
!style="background-color: #f9f9f9"| 1.010 (10)
| b1.010 (10)||R10L||R10W||R10D||R10||MM2||XMM10||YMM10||SS||CR10||DR10
|R10L||R10W||R10D||R10||-||MMX2||XMM10||YMM10||SS||CR10||DR10
|-
!style="background-color: #f9f9f9"| 1.011 (11)
| b1.011 (11)||R11L||R11W||R11D||R11||MM3||XMM11||YMM11||DS||CR11||DR11
|R11L||R11W||R11D||R11||-||MMX3||XMM11||YMM11||DS||CR11||DR11
|-
!style="background-color: #f9f9f9"| 1.100 (12)
| b1.100 (12)||R12L||R12W||R12D||R12||MM4||XMM12||YMM12||FS||CR12||DR12
|R12L||R12W||R12D||R12||-||MMX4||XMM12||YMM12||FS||CR12||DR12
|-
!style="background-color: #f9f9f9"| 1.101 (13)
| b1.101 (13)||R13L||R13W||R13D||R13||MM5||XMM13||YMM13||GS||CR13||DR13
|R13L||R13W||R13D||R13||-||MMX5||XMM13||YMM13||GS||CR13||DR13
|-
!style="background-color: #f9f9f9"| 1.110 (14)
| b1.110 (14)||R14L||R14W||R14D||R14||MM6||XMM14||YMM14||invalid||CR14||DR14
|R14L||R14W||R14D||R14||-||MMX6||XMM14||YMM14||-||CR14||DR14
|-
!style="background-color: #f9f9f9"| 1.111 (15)
| b1.111 (15)||R15L||R15W||R15D||R15||MM7||XMM15||YMM15||invalid||CR15||DR15
|R15L||R15W||R15D||R15||-||MMX7||XMM15||YMM15||-||CR15||DR15
|}
</div>
<small id="Table1Note1">1: When any REX prefix is used, SPL, BPL, SIL and DIL are used. Otherwise, without any REX prefix AH, CH, DH and BH are used.</small>
 
== Legacy Prefixes ==
Each instruction can have up to four prefixes. Sometimes a prefix is required for the instruction while it loses it'sits original meaning (i.e. a 'mandatory prefix'). The following prefixes can be used, the order does not matter:
* Prefix group 1
** 0xF0: LOCK prefix
Line 94 ⟶ 123:
The default operand-size and address-size can be overridden using these prefix. See the following table:
 
{| {{wikitable|background-color: white}}
!style="background-color: #f9f9f9"| &nbsp;
! Operating mode
!style="background-color: #f9f9f9"| CS.d
! CS.d
!style="background-color: #f9f9f9"| REX.W
! 0x66 operand prefix
!style="background-color: #f9f9f9"| Prefix (0x66 if operand, 0x67 if address)
! 0x67 address prefix
!style="background-color: #f9f9f9"| Operand size
! REX.w
!style="background-color: #f9f9f9"| Address size
! Operand-size
! Address-size
|-
| Real mode||N/A||N/A||N/A||N/A||16-bit||16-bit
|-
| Virtual 8086 mode||N/A||N/A||N/A||N/A||16-bit||16-bit
|-
| rowspan="8" | Protected mode /<br />Long compatibility mode||0||no||no||N/A||16-bit||16-bit
|-
| 0||no||yes||N/A||16-bit||32-bit
|-
| 0||yes||no||N/A||32-bit||16-bit
|-
| 0||yes||yes||N/A||32-bit||32-bit
|-
!style="background-color: #f9f9f9" rowspan="2"| Real mode /<br />Virtual 8086 mode
| 1||no||no||N/A||32-bit||32-bit
| N/A||N/A||{{No}}||16-bit||16-bit
|-
| 1||no||yesN/A||N/A||{{Yes}}||32-bit||1632-bit
|-
! style="background-color: #f9f9f9" rowspan="4" | Protected mode /<br />Long compatibility mode
| 1||yes||no||N/A||16-bit||32-bit
| {{No|0}}||N/A||{{No}}||16-bit||16-bit
|-
| 1{{No||yes||yes0}}||N/A||16{{Yes}}||32-bit||1632-bit
|-
| rowspan="6" {{Yes| Long 64-bit mode1}}||ignoredN/A||no||no||0{{No}}||32-bit||6432-bit
|-
| {{Yes|1}}||N/A||{{Yes}}||16-bit||16-bit
| ignored||no||yes||0||32-bit<span style="vertical-align: super">[[#Table2Note1|1]]</span>||32-bit
|-
! style="background-color: #f9f9f9" rowspan="4" | Long 64-bit mode
| ignored||yes||no||0||16-bit||64-bit
| Ignored||{{No|0}}||{{No}}||32-bit||64-bit
|-
| ignoredIgnored||yes{{No|0}}|yes||0{{Yes}}||16-bit||32-bit
|-
| ignoredIgnored||ignored{{Yes|1}}|no||1{{No}}||64-bit<span style="vertical-align: super">[[#Table2Note1|1]]</span>||64-bit
|-
| ignoredIgnored||ignored{{Yes|1}}|yes||1{{Yes}}||64-bit||32-bit
|}
<small id="Table2Note1">1: Certain instructions default to (or are fixed at) 64-bit operands and do not need the REX prefix for this, see [[#Usage|this table]].</small>
Line 197 ⟶ 216:
+---+---+---+---+---+---+---+---+
</pre>
{| {{wikitable|background-color:white;}}
! style="background-color:#f9f9f9;" | Field
! Field
! style="background-color:#f9f9f9;" | Length
! Length
! style="background-color:#f9f9f9;" | Description
|-
!style="background-color:#f9f9f9;"| 0100
| b0100||4 bits||Fixed bit pattern
|4 bits||Fixed bit pattern
|-
!style="background-color:#f9f9f9;"| W
| W||1 bit||When 1, a 64-bit operand size is used. Otherwise, when 0, the default operand size is used (which is 32-bit for most but not all instructions, see [[#Operand-size and address-size override prefix|this table]]).
|1 bit||When 1, a 64-bit operand size is used. Otherwise, when 0, the default operand size is used (which is 32-bit for most but not all instructions, see [[#Operand-size and address-size override prefix|this table]]).
|-
!style="background-color:#f9f9f9;"| R
| R||1 bit||This 1-bit value is an extension to the ''MODRM.reg'' field. See [[#Registers|Registers]].
|1 bit||This 1-bit value is an extension to the ''MODRM.reg'' field. See [[#Registers|Registers]].
|-
!style="background-color:#f9f9f9;"| X
| X||1 bit||This 1-bit value is an extension to the ''SIB.index'' field. See [[#64-bit addressing|64-bit addressing]].
|1 bit||This 1-bit value is an extension to the ''SIB.index'' field. See [[#64-bit addressing|64-bit addressing]].
|-
!style="background-color:#f9f9f9;"| B
| B||1 bit||This 1-bit value is an extension to the ''MODRM.rm'' field or the ''SIB.base'' field. See [[#64-bit addressing|64-bit addressing]].
|1 bit||This 1-bit value is an extension to the ''MODRM.rm'' field or the ''SIB.base'' field. See [[#64-bit addressing|64-bit addressing]].
|}
 
Because the first four bits always equal 4, the existence of the REX prefix wipes out opcodes 0x40-0x4F, which were previously individual increment and decrement instructions for all eight registers. The Intel 64 and IA-32 Architectures
Software Developer’s Manual volume 2 states "The single-byte-opcode forms of the INC/DEC instructions are not available in 64-bit mode. INC/DEC functionality is still available using ModR/M forms of the same instructions (opcodes FF/0 and FF/1)."
 
==== Opcode ====
Line 235 ⟶ 262:
There are many VEX and XOP instructions, all of which can be encoded using the three byte VEX/XOP escape prefix. The VEX and XOP escape prefixes use fields with the following semantics:
 
{| {{wikitable|background-color:white;}}
!style="background-color:#f9f9f9;"| Field
! Field
!style="background-color:#f9f9f9;"| Length
! Length
!style="background-color:#f9f9f9;"| Description
|-
!style="background-color:#f9f9f9; text-align: left; vertical-align: top;"| VEX/XOP prefix
| VEX/XOP prefix||8 bits||Prefix.
|style="vertical-align: top;"|8 bits||Prefix.
{| {{wikitable}}
! Prefix
Line 252 ⟶ 280:
|}
|-
!style="background-color:#f9f9f9; text-align: left; vertical-align: top;"| ~R
| ~R||1 bit||This 1-bit value is an 'inverted' extension to the ''MODRM.reg'' field. The inverse of REX.R. See [[#Registers|Registers]].
|style="vertical-align: top;"|1 bit||This 1-bit value is an 'inverted' extension to the ''MODRM.reg'' field. The inverse of REX.R. See [[#Registers|Registers]].
|-
!style="background-color:#f9f9f9; text-align: left; vertical-align: top;"| ~X
| ~X||1 bit||This 1-bit value is an 'inverted' extension to the ''SIB.index'' field. The inverse of REX.X. See [[#64-bit addressing|64-bit addressing]].
|style="vertical-align: top;"|1 bit||This 1-bit value is an 'inverted' extension to the ''SIB.index'' field. The inverse of REX.X. See [[#64-bit addressing|64-bit addressing]].
|-
!style="background-color:#f9f9f9; text-align: left; vertical-align: top;"| ~B
| ~B||1 bit||This 1-bit value is an 'inverted' extension to the ''MODRM.rm'' field or the ''SIB.base'' field. The inverse of REX.B. See [[#64-bit addressing|64-bit addressing]].
|style="vertical-align: top;"|1 bit||This 1-bit value is an 'inverted' extension to the ''MODRM.rm'' field or the ''SIB.base'' field. The inverse of REX.B. See [[#64-bit addressing|64-bit addressing]].
|-
!style="background-color:#f9f9f9; text-align: left; vertical-align: top;"| map_select
| map_select||5 bits||Specifies the opcode map to use.
|style="vertical-align: top;"|5 bits||Specifies the opcode map to use.
|-
!style="background-color:#f9f9f9; text-align: left; vertical-align: top;"| W/E
| W/E||1 bit||For integer instructions: when 1, a 64-bit operand size is used; otherwise, when 0, the default operand size is used (equivalent with REX.W). For non-integer instructions, this bit is a general opcode extension bit.
|style="vertical-align: top;"|1 bit||For integer instructions: when 1, a 64-bit operand size is used; otherwise, when 0, the default operand size is used (equivalent with REX.W). For non-integer instructions, this bit is a general opcode extension bit.
|-
!style="background-color:#f9f9f9; text-align: left; vertical-align: top;"| ~vvvv
| ~vvvv||4 bits||An additional operand for the instruction. The value of the XMM or YMM register (see [[#Registers|Registers]]) is 'inverted'.
|style="vertical-align: top;"|4 bits||An additional operand for the instruction. The value of the XMM or YMM register (see [[#Registers|Registers]]) is 'inverted'.
|-
!style="background-color:#f9f9f9; text-align: left; vertical-align: top;"| L
| L||1 bit||When 0, a 128-bit vector lengh is used. Otherwise, when 1, a 256-bit vector length is used.
|style="vertical-align: top;"|1 bit||When 0, a 128-bit vector lengh is used. Otherwise, when 1, a 256-bit vector length is used.
|-
!style="background-color:#f9f9f9; text-align: left; vertical-align: top;"| pp
| pp||2 bits||Specifies an implied mandatory prefix for the opcode.
|style="vertical-align: top;"|2 bits||Specifies an implied mandatory prefix for the opcode.
{| {{wikitable}}
! Value (binary)
! Implied mandatory prefix
|-
| b0000||none
|-
| b0101||0x66
|-
| b1010||0xF3
|-
| b1111||0xF2
|}
|}
Line 299 ⟶ 335:
+---+---+---+---+---+---+---+---+ +---+---+---+---+---+---+---+---+ +---+---+---+---+---+---+---+---+
</pre>
 
The AMD64 Architecture Programmer’s Manual Volume 6 states that the map_select field must be equal to or greater than 8, to differentiate the XOP prefix from the POP instruction that formerly used opcode 0x8F.
 
==== Two byte VEX escape prefix ====
Line 332 ⟶ 370:
+---+---+---+---+---+---+---+---+
</pre>
{| {{wikitable|background-color: white}}
!style="background-color:#f9f9f9;"| Field
! Field
!style="background-color:#f9f9f9;"| Length
! Length
!style="background-color:#f9f9f9;"| Description
|-
!style="background-color:#f9f9f9; text-align: left; vertical-align: top;"| MODRM.mod
| MODRM.mod||2 bits||In general, when this field is b11, then register-direct addressing mode is used; otherwise register-indirect addressing mode is used.
|style="vertical-align: top;"|2 bits||In general, when this field is b11, then register-direct addressing mode is used; otherwise register-indirect addressing mode is used.
|-
!style="background-color:#f9f9f9; text-align: left; vertical-align: top;"| MODRM.reg
| MODRM.reg||3 bits||This field can have one of two values:
|style="vertical-align: top;"|3 bits||This field can have one of two values:
* A 3-bit opcode extension, which is used by some instructions but has no further meaning other than distinguishing the instruction from other instructions.
* A 3-bit register reference, which can be used as the source or the destination of an instruction (depending on the instruction). The referenced register depends on the [[#Operand-size and address-size override prefix|operand-size]] of the instruction and the instruction itself. See [[#Registers|Registers]] for the values to use for each of the registers. The REX.R, VEX.~R or XOP.~R field can extend this field with 1 most-significant bit to 4 bits total.
|-
!style="background-color:#f9f9f9; text-align: left; vertical-align: top;"| MODRM.rm
| MODRM.rm||3 bits||Specifies a direct or indirect register operand, optionally with a displacement. The REX.B, VEX.~B or XOP.~B field can extend this field with 1 most-significant bit to 4 bits total.
|style="vertical-align: top;"|3 bits||Specifies a direct or indirect register operand, optionally with a displacement. The REX.B, VEX.~B or XOP.~B field can extend this field with 1 most-significant bit to 4 bits total.
|}
 
Line 363 ⟶ 404:
|-
! 00
| style="background-color: white" |[BX] +[ SI]
| style="background-color: white" |[BX] +[ DI]
| style="background-color: white" |[BP] +[ SI]
| style="background-color: white" |[BP] +[ DI]
| style="background-color: white" |[SI]
| style="background-color: white" |[DI]
| style="background-color: white" |[disp16]
| style="background-color: white" |[BX]
|-
! 01
| style="background-color: white" |[BX] +[ SI] + disp8]
| style="background-color: white" |[BX] +[ DI] + disp8]
| style="background-color: white" |[BP] +[ SI] + disp8]
| style="background-color: white" |[BP] +[ DI] + disp8]
| style="background-color: white" |[SI] + disp8]
| style="background-color: white" |[DI] + disp8]
| style="background-color: white" |[BP] + disp8]
| style="background-color: white" |[BX] + disp8]
|-
! 10
| style="background-color: white" |[BX] +[ SI] + disp16]
| style="background-color: white" |[BX] +[ DI] + disp16]
| style="background-color: white" |[BP] +[ SI] + disp16]
| style="background-color: white" |[BP] +[ DI] + disp16]
| style="background-color: white" |[SI] + disp16]
| style="background-color: white" |[DI] + disp16]
| style="background-color: white" |[BP] + disp16]
| style="background-color: white" |[BX] + disp16]
|-
! 11
Line 423 ⟶ 464:
! 00
| style="background-color: white" colspan="4"|[r/m]
| style="background-color: white" |&#91;[[#SIB|SIB]]]
| style="background-color: white" |[&nbsp#91;[[#RIP.2FEIP-relative_addressing|RIP/EIP]]]<span style="vertical-align: super">[[#Table8Note1|1]],[[#Table8Note2|2]]</span> + disp32]
| style="background-color: white" colspan="6"|[r/m]
| style="background-color: white" |&#91;[[#SIB|SIB]]]
| style="background-color: white" |[&nbsp#91;[[#RIP.2FEIP-relative_addressing|RIP/EIP]]]<span style="vertical-align: super">[[#Table8Note1|1]],[[#Table8Note2|2]]</span> + disp32]
| style="background-color: white" colspan="2"|[r/m]
|-
! 01
| style="background-color: white" colspan="4"|[r/m] + disp8]
| style="background-color: white" |&#91;[[#SIB|SIB]] + disp8]
| style="background-color: white" colspan="7"|[r/m] + disp8]
| style="background-color: white" |&#91;[[#SIB|SIB]] + disp8]
| style="background-color: white" colspan="3"|[r/m] + disp8]
|-
! 10
| style="background-color: white" colspan="4"|[r/m] + disp32]
| style="background-color: white" |&#91;[[#SIB|SIB]] + disp32]
| style="background-color: white" colspan="7"|[r/m] + disp32]
| style="background-color: white" |&#91;[[#SIB|SIB]] + disp32]
| style="background-color: white" colspan="3"|[r/m] + disp32]
|-
! 11
Line 448 ⟶ 489:
|}
</div>
<small id="Table8Note1">1: In protected/compatibility mode, this is just ''disp32'', but in long mode this is ''[RIP]+disp32'' (for 64-bit addresses) or ''[EIP]+disp32'' (for 32-bit addresses, i.e. with address-size override prefix, [http://objectmix.com/asm-x86-asm-370/69055-effect-address-size-prefix-rip-relative-addressing.html see here]).</small><br />
<small id="Table8Note2">2: In long mode, to encode ''disp32'' as in protected/compatibility mode, use the SIB byte.</small>
 
Line 462 ⟶ 503:
+---+---+---+---+---+---+---+---+
</pre>
{| {{wikitable|background-color: white}}
!style="background-color:#f9f9f9;"| Field
! Field
!style="background-color:#f9f9f9;"| Length
! Length
!style="background-color:#f9f9f9;"| Description
|-
!style="background-color:#f9f9f9; text-align: left; vertical-align: top;"|SIB.scale
| SIB.scale ||2 bits||This field indicates the scaling factor of SIB.index, where ''s'' (as used in the tables) equals 2<span style="vertical-align: super;">SIB.scale</span>.
|style="vertical-align: top;"|2 bits||This field indicates the scaling factor of SIB.index, where ''s'' (as used in the tables) equals 2<span style="vertical-align: super;">SIB.scale</span>.
{| {{wikitable}}
! SIB.scale
Line 481 ⟶ 523:
|}
|-
!style="background-color:#f9f9f9; text-align: left; vertical-align: top;"|SIB.index
| SIB.index||3 bits||The index register to use. See [[#Registers|Registers]] for the values to use for each of the registers. The REX.X, VEX.~X or XOP.~X field can extend this field with 1 most-significant bit to 4 bits total.
|style="vertical-align: top;"|3 bits||The index register to use. See [[#Registers|Registers]] for the values to use for each of the registers. The REX.X, VEX.~X or XOP.~X field can extend this field with 1 most-significant bit to 4 bits total.
|-
!style="background-color:#f9f9f9; text-align: left; vertical-align: top;"|SIB.base
| SIB.base||3 bits||The base register to use. See [[#Registers|Registers]] for the values to use for each of the registers. The REX.B, VEX.~B or XOP.~B field can extend this field with 1 most-significant bit to 4 bits total.
|style="vertical-align: top;"|3 bits||The base register to use. See [[#Registers|Registers]] for the values to use for each of the registers. The REX.B, VEX.~B or XOP.~B field can extend this field with 1 most-significant bit to 4 bits total.
|}
 
Line 512 ⟶ 556:
|-
! rowspan="16" | 00 !! style="text-align: left;" | 0.000 AX
| style="background-color: white" rowspan="4" colspan="5"|[base] + ([index] * s)]
| style="background-color: white" rowspan="4"|([(index] * s)<br />+ disp32]
| style="background-color: white" rowspan="4" colspan="7" |[base] + ([index] * s)]
| style="background-color: white" rowspan="4"|([(index] * s)<br />+ disp32]
| style="background-color: white" rowspan="4" colspan="2"|[base] + ([index] * s)]
|-
! style="text-align: left;" | 0.001 CX
Line 526 ⟶ 570:
! style="text-align: left;" | 0.100<span style="vertical-align: super">[[#Table10Note2|2]]</span> SP
| style="background-color: white" colspan="5"|[base]
| style="background-color: white"| [disp32]
| style="background-color: white" colspan="7"|[base]
| style="background-color: white"| [disp32]
| style="background-color: white" colspan="2"|[base]
|-
! style="text-align: left;" | 0.101 BP
| style="background-color: white" rowspan="11" colspan="5"|[base] + ([index] * s)]
| style="background-color: white" rowspan="11"|([(index] * s)<br />+ disp32]
| style="background-color: white" rowspan="11" colspan="7"|[base] + ([index] * s)]
| style="background-color: white" rowspan="11"|([(index] * s)<br />+ disp32]
| style="background-color: white" rowspan="11" colspan="2"|[base] + ([index] * s)]
|-
! style="text-align: left;" | 0.110 SI
Line 582 ⟶ 626:
|-
! rowspan="16" | 01 !! style="text-align: left;" | 0.000 AX
| style="background-color: white" rowspan="4" colspan="16"|[base] + ([index] * s) + disp8]
|-
! style="text-align: left;" | 0.001 CX
Line 591 ⟶ 635:
|-
! style="text-align: left;" | 0.100<span style="vertical-align: super">[[#Table10Note2|2]]</span> SP
| style="background-color: white" colspan="16"|[base] + disp8]
|-
! style="text-align: left;" | 0.101 BP
| style="background-color: white" rowspan="11" colspan="16"|[base] + ([index] * s) + disp8]
|-
! style="text-align: left;" | 0.110 SI
Line 640 ⟶ 684:
|-
! rowspan="16" | 10 !! style="text-align: left;" | 0.000 AX
| style="background-color: white" rowspan="4" colspan="16"|[base] + ([index] * s) + disp32]
|-
! style="text-align: left;" | 0.001 CX
Line 649 ⟶ 693:
|-
! style="text-align: left;" | 0.100<span style="vertical-align: super">[[#Table10Note2|2]]</span> SP
| style="background-color: white" colspan="16"|[base] + disp32]
|-
! style="text-align: left;" | 0.101 BP
| style="background-color: white" rowspan="11" colspan="16"|[base] + ([index] * s) + disp32]
|-
! style="text-align: left;" | 0.110 SI
Line 688 ⟶ 732:
== See Also ==
=== External References ===
* AMD64 Architecture Programmer's Manual [httphttps://www.amd.com/us-ensystem/assetsfiles/content_type/white_papers_and_tech_docsTechDocs/24594.pdf Volume 3: General-Purpose and System Instructions]
* [http://www.intel.com/products/processor/manuals/ Intel 64 and IA-32 Architectures Software Developer's Manuals]
 
[[Category:X86 CPU]]
[[Category:X86-64]]
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