|
* [[#Displacement|Displacement]] (1, 2, 4 or 8 bytes, if required)
* [[#Immediate|Immediate]] (1, 2, 4 or 8 bytes, if required)
== Registers ==
The registers are encoded using the 4-bit values in the X.Reg column of the following table. ''X.Reg'' is in binary.
<div style="font-size: smaller">
{| {{wikitable|background: white;}}
!style="background-color: #f9f9f9"| X.Reg
!style="background-color: #f9f9f9"| 8-bit GP
!style="background-color: #f9f9f9"| 16-bit GP
!style="background-color: #f9f9f9"| 32-bit GP
!style="background-color: #f9f9f9"| 64-bit GP
!style="background-color: #f9f9f9"| 80-bit x87
!style="background-color: #f9f9f9"| 64-bit MMX
!style="background-color: #f9f9f9"| 128-bit XMM
!style="background-color: #f9f9f9"| 256-bit YMM
!style="background-color: #f9f9f9"| 16-bit Segment
!style="background-color: #f9f9f9"| 32-bit Control
!style="background-color: #f9f9f9"| 32-bit Debug
|-
!style="background-color: #f9f9f9"| 0.000 (0)
|AL||AX||EAX||RAX||ST0||MMX0||XMM0||YMM0||ES||CR0||DR0
|-
!style="background-color: #f9f9f9"| 0.001 (1)
|CL||CX||ECX||RCX||ST1||MMX1||XMM1||YMM1||CS||CR1||DR1
|-
!style="background-color: #f9f9f9"| 0.010 (2)
|DL||DX||EDX||RDX||ST2||MMX2||XMM2||YMM2||SS||CR2||DR2
|-
!style="background-color: #f9f9f9"| 0.011 (3)
|BL||BX||EBX||RBX||ST3||MMX3||XMM3||YMM3||DS||CR3||DR3
|-
!style="background-color: #f9f9f9"| 0.100 (4)
|AH, SPL<span style="vertical-align: super">[[#Table1Note1|1]]</span>||SP||ESP||RSP||ST4||MMX4||XMM4||YMM4||FS||CR4||DR4
|-
!style="background-color: #f9f9f9"| 0.101 (5)
|CH, BPL<span style="vertical-align: super">[[#Table1Note1|1]]</span>||BP||EBP||RBP||ST5||MMX5||XMM5||YMM5||GS||CR5||DR5
|-
!style="background-color: #f9f9f9"| 0.110 (6)
|DH, SIL<span style="vertical-align: super">[[#Table1Note1|1]]</span>||SI||ESI||RSI||ST6||MMX6||XMM6||YMM6||-||CR6||DR6
|-
!style="background-color: #f9f9f9"| 0.111 (7)
|BH, DIL<span style="vertical-align: super">[[#Table1Note1|1]]</span>||DI||EDI||RDI||ST7||MMX7||XMM7||YMM7||-||CR7||DR7
|-
!style="background-color: #f9f9f9"| 1.000 (8)
|R8L||R8W||R8D||R8||-||MMX0||XMM8||YMM8||ES||CR8||DR8
|-
!style="background-color: #f9f9f9"| 1.001 (9)
|R9L||R9W||R9D||R9||-||MMX1||XMM9||YMM9||CS||CR9||DR9
|-
!style="background-color: #f9f9f9"| 1.010 (10)
|R10L||R10W||R10D||R10||-||MMX2||XMM10||YMM10||SS||CR10||DR10
|-
!style="background-color: #f9f9f9"| 1.011 (11)
|R11L||R11W||R11D||R11||-||MMX3||XMM11||YMM11||DS||CR11||DR11
|-
!style="background-color: #f9f9f9"| 1.100 (12)
|R12L||R12W||R12D||R12||-||MMX4||XMM12||YMM12||FS||CR12||DR12
|-
!style="background-color: #f9f9f9"| 1.101 (13)
|R13L||R13W||R13D||R13||-||MMX5||XMM13||YMM13||GS||CR13||DR13
|-
!style="background-color: #f9f9f9"| 1.110 (14)
|R14L||R14W||R14D||R14||-||MMX6||XMM14||YMM14||-||CR14||DR14
|-
!style="background-color: #f9f9f9"| 1.111 (15)
|R15L||R15W||R15D||R15||-||MMX7||XMM15||YMM15||-||CR15||DR15
|}
</div>
<small id="Table1Note1">1: When any REX prefix is used, SPL, BPL, SIL and DIL are used. Otherwise, without any REX prefix AH, CH, DH and BH are used.</small>
== Legacy Prefixes ==
Each instruction can have up to four prefixes. Sometimes a prefix is required for the instruction while it loses it'sits original meaning (i.e. a 'mandatory prefix'). The following prefixes can be used, the order does not matter:
* Prefix group 1
** 0xF0: LOCK prefix
The default operand-size and address-size can be overridden using these prefix. See the following table:
{| {{wikitable|background-color: white}}
!style="background-color: #f9f9f9"|
! Operating mode
!style="background-color: #f9f9f9"| CS.d
! CS.d
!style="background-color: #f9f9f9"| REX.W
! 0x66 operand prefix
!style="background-color: #f9f9f9"| Prefix (0x66 if operand, 0x67 if address)
! 0x67 address prefix
!style="background-color: #f9f9f9"| Operand size
! REX.w
!style="background-color: #f9f9f9"| Address size
! Operand-size
! Address-size
|-
!style="background-color: #f9f9f9" rowspan="2"| Real mode /<br />Virtual 8086 mode
| Real mode||N/A||N/A||N/A||N/A||16-bit||16-bit
| N/A||N/A||{{No}}||16-bit||16-bit
|-
| Virtual 8086 mode||N/A||N/A||N/A||N/A{{Yes}}||1632-bit||1632-bit
|-
|! style="background-color: #f9f9f9" rowspan="84" | Protected mode /<br />Long compatibility mode||0||no||no||N/A||16-bit||16-bit
| {{No|0}}||N/A||{{No}}||16-bit||16-bit
|-
| {{No|0||no||yes}}||N/A||16{{Yes}}||32-bit||32-bit
|-
| 0{{Yes||yes||no1}}||N/A||{{No}}||32-bit||1632-bit
|-
| 0{{Yes||yes||yes1}}||N/A||32{{Yes}}||16-bit||3216-bit
|-
! style="background-color: #f9f9f9" rowspan="4" | Long 64-bit mode
| 1||no||no||N/A||32-bit||32-bit
| Ignored||{{No|0}}||{{No}}||32-bit||64-bit
|-
| 1Ignored||no{{No|0}}|yes|{{Yes}}|N/A||3216-bit||1632-bit
|-
| Ignored||{{Yes|1}}||{{No}}||64-bit<span style="vertical-align: super">[[#Table2Note1|1]]</span>||64-bit
| 1||yes||no||N/A||16-bit||32-bit
|-
| 1Ignored||yes{{Yes||yes1}}||N/A{{Yes}}||1664-bit||1632-bit
|-
| rowspan="6" | Long 64-bit mode||ignored||no||no||0||32-bit||64-bit
|-
| ignored||no||yes||0||32-bit<span style="vertical-align: super">[[#Table1Note1|1]]</span>||32-bit
|-
| ignored||yes||no||0||16-bit||64-bit
|-
| ignored||yes||yes||0||16-bit||32-bit
|-
| ignored||ignored||no||1||64-bit<span style="vertical-align: super">[[#Table1Note1|1]]</span>||64-bit
|-
| ignored||ignored||yes||1||64-bit||32-bit
|}
<small id="Table1Note1Table2Note1">1: Certain instructions default to (or are fixed at) 64-bit operands and do not need the REX prefix for this, see [[#Usage|this table]].</small>
==== NASM ====
+---+---+---+---+---+---+---+---+
</pre>
{| {{wikitable|background-color:white;}}
! style="background-color:#f9f9f9;" | Field
! Field
! style="background-color:#f9f9f9;" | Length
! Length
! style="background-color:#f9f9f9;" | Description
|-
!style="background-color:#f9f9f9;"| 0100
| b0100||4 bits||Fixed bit pattern
|4 bits||Fixed bit pattern
|-
!style="background-color:#f9f9f9;"| W
| W||1 bit||When 1, a 64-bit operand size is used. Otherwise, when 0, the default operand size is used (which is 32-bit for most but not all instructions, see [[#Operand-size and address-size override prefix|this table]]).
|1 bit||When 1, a 64-bit operand size is used. Otherwise, when 0, the default operand size is used (which is 32-bit for most but not all instructions, see [[#Operand-size and address-size override prefix|this table]]).
|-
!style="background-color:#f9f9f9;"| R
| R||1 bit||This 1-bit value is an extension to the ''MODRM.reg'' field. See [[#Registers|Registers]].
|1 bit||This 1-bit value is an extension to the ''MODRM.reg'' field. See [[#Registers|Registers]].
|-
!style="background-color:#f9f9f9;"| X
| X||1 bit||This 1-bit value is an extension to the ''SIB.index'' field. See [[#64-bit addressing|64-bit addressing]].
|1 bit||This 1-bit value is an extension to the ''SIB.index'' field. See [[#64-bit addressing|64-bit addressing]].
|-
!style="background-color:#f9f9f9;"| B
| B||1 bit||This 1-bit value is an extension to the ''MODRM.rm'' field or the ''SIB.base'' field. See [[#64-bit addressing|64-bit addressing]].
|1 bit||This 1-bit value is an extension to the ''MODRM.rm'' field or the ''SIB.base'' field. See [[#64-bit addressing|64-bit addressing]].
|}
Because the first four bits always equal 4, the existence of the REX prefix wipes out opcodes 0x40-0x4F, which were previously individual increment and decrement instructions for all eight registers. The Intel 64 and IA-32 Architectures
Software Developer’s Manual volume 2 states "The single-byte-opcode forms of the INC/DEC instructions are not available in 64-bit mode. INC/DEC functionality is still available using ModR/M forms of the same instructions (opcodes FF/0 and FF/1)."
==== Opcode ====
* the instruction has only its VEX/XOP opcode and no legacy opcode; or
* 256-bit YMM registers are used; or
* more than three operands are used (e.g. ''nondestructive-source operations''); or
* when using 128-bit XMM destination registers, bits 128-255 of the corresponding YMM register must be cleared.
There are many VEX and XOP instructions, all of which can be encoded using the three byte VEX/XOP escape prefix. The VEX and XOP escape prefixes use fields with the following semantics:
{| {{wikitable|background-color:white;}}
!style="background-color:#f9f9f9;"| Field
! Field
!style="background-color:#f9f9f9;"| Length
! Length
!style="background-color:#f9f9f9;"| Description
|-
!style="background-color:#f9f9f9; text-align: left; vertical-align: top;"| VEX/XOP prefix
| VEX/XOP prefix||8 bits||Prefix.
|style="vertical-align: top;"|8 bits||Prefix.
{| {{wikitable}}
! Prefix
|}
|-
!style="background-color:#f9f9f9; text-align: left; vertical-align: top;"| ~R
| ~R||1 bit||This 1-bit value is an 'inverted' extension to the ''MODRM.reg'' field. The inverse of REX.R. See [[#Registers|Registers]].
|style="vertical-align: top;"|1 bit||This 1-bit value is an 'inverted' extension to the ''MODRM.reg'' field. The inverse of REX.R. See [[#Registers|Registers]].
|-
!style="background-color:#f9f9f9; text-align: left; vertical-align: top;"| ~X
| ~X||1 bit||This 1-bit value is an 'inverted' extension to the ''SIB.index'' field. The inverse of REX.X. See [[#64-bit addressing|64-bit addressing]].
|style="vertical-align: top;"|1 bit||This 1-bit value is an 'inverted' extension to the ''SIB.index'' field. The inverse of REX.X. See [[#64-bit addressing|64-bit addressing]].
|-
!style="background-color:#f9f9f9; text-align: left; vertical-align: top;"| ~B
| ~B||1 bit||This 1-bit value is an 'inverted' extension to the ''MODRM.rm'' field or the ''SIB.base'' field. The inverse of REX.B. See [[#64-bit addressing|64-bit addressing]].
|style="vertical-align: top;"|1 bit||This 1-bit value is an 'inverted' extension to the ''MODRM.rm'' field or the ''SIB.base'' field. The inverse of REX.B. See [[#64-bit addressing|64-bit addressing]].
|-
!style="background-color:#f9f9f9; text-align: left; vertical-align: top;"| map_select
| map_select||5 bits||Specifies the opcode map to use.
|style="vertical-align: top;"|5 bits||Specifies the opcode map to use.
|-
!style="background-color:#f9f9f9; text-align: left; vertical-align: top;"| W/E
| W/E||1 bit||For integer instructions: when 1, a 64-bit operand size is used; otherwise, when 0, the default operand size is used (equivalent with REX.W). For non-integer instructions, this bit is a general opcode extension bit.
|style="vertical-align: top;"|1 bit||For integer instructions: when 1, a 64-bit operand size is used; otherwise, when 0, the default operand size is used (equivalent with REX.W). For non-integer instructions, this bit is a general opcode extension bit.
|-
!style="background-color:#f9f9f9; text-align: left; vertical-align: top;"| ~vvvv
| ~vvvv||4 bits||An additional operand for the instruction. The value of the XMM or YMM register (see [[#Registers|Registers]]) is 'inverted'.
|style="vertical-align: top;"|4 bits||An additional operand for the instruction. The value of the XMM or YMM register (see [[#Registers|Registers]]) is 'inverted'.
|-
!style="background-color:#f9f9f9; text-align: left; vertical-align: top;"| L
| L||1 bit||When 0, a 128-bit vector lengh is used. Otherwise, when 1, a 256-bit vector length is used.
|style="vertical-align: top;"|1 bit||When 0, a 128-bit vector lengh is used. Otherwise, when 1, a 256-bit vector length is used.
|-
!style="background-color:#f9f9f9; text-align: left; vertical-align: top;"| pp
| pp||2 bits||Specifies an implied mandatory prefix for the opcode.
|style="vertical-align: top;"|2 bits||Specifies an implied mandatory prefix for the opcode.
{| {{wikitable}}
! Value (binary)
! Implied mandatory prefix
|-
| b0000||none
|-
| b0101||0x66
|-
| b1010||0xF3
|-
| b1111||0xF2
|}
|}
+---+---+---+---+---+---+---+---+ +---+---+---+---+---+---+---+---+ +---+---+---+---+---+---+---+---+
</pre>
The AMD64 Architecture Programmer’s Manual Volume 6 states that the map_select field must be equal to or greater than 8, to differentiate the XOP prefix from the POP instruction that formerly used opcode 0x8F.
==== Two byte VEX escape prefix ====
+---+---+---+---+---+---+---+---+
</pre>
{| {{wikitable|background-color: white}}
!style="background-color:#f9f9f9;"| Field
! Field
!style="background-color:#f9f9f9;"| Length
! Length
!style="background-color:#f9f9f9;"| Description
|-
!style="background-color:#f9f9f9; text-align: left; vertical-align: top;"| MODRM.mod
| MODRM.mod||2 bits||In general, when this field is b11, then register-direct addressing mode is used; otherwise register-indirect addressing mode is used.
|style="vertical-align: top;"|2 bits||In general, when this field is b11, then register-direct addressing mode is used; otherwise register-indirect addressing mode is used.
|-
!style="background-color:#f9f9f9; text-align: left; vertical-align: top;"| MODRM.reg
| MODRM.reg||3 bits||This field can have one of two values:
|style="vertical-align: top;"|3 bits||This field can have one of two values:
* A 3-bit opcode extension, which is used by some instructions but has no further meaning other than distinguishing the instruction from other instructions.
* A 3-bit register reference, which can be used as the source or the destination of an instruction (depending on the instruction). The referenced register depends on the [[#Operand-size and address-size override prefix|operand-size]] of the instruction and the instruction itself. See [[#Registers|Registers]] for the values to use for each of the registers. The REX.R, VEX.~R or XOP.~R field can extend this field with 1 most-significant bit to 4 bits total.
|-
!style="background-color:#f9f9f9; text-align: left; vertical-align: top;"| MODRM.rm
| MODRM.rm||3 bits||Specifies a direct or indirect register operand, optionally with a displacement. The REX.B, VEX.~B or XOP.~B field can extend this field with 1 most-significant bit to 4 bits total.
|style="vertical-align: top;"|3 bits||Specifies a direct or indirect register operand, optionally with a displacement. The REX.B, VEX.~B or XOP.~B field can extend this field with 1 most-significant bit to 4 bits total.
|}
==== Registers ====
The registers are encoded using the 4-bit values in the X.Reg column of the following table.
{| {{wikitable}}
! X.Reg!! 8-bit GP!! 16-bit GP!! 32-bit GP!! 64-bit GP!! 64-bit MMX!! 128-bit XMM!! 256-bit YMM!! 16-bit Segment!! 32-bit Control!! 32-bit Debug
|-
| b0.000 (0)||AL||AX||EAX||RAX||MM0||XMM0||YMM0||ES||CR0||DR0
|-
| b0.001 (1)||CL||CX||ECX||RCX||MM1||XMM1||YMM1||CS||CR1||DR1
|-
| b0.010 (2)||DL||DX||EDX||RDX||MM2||XMM2||YMM2||SS||CR2||DR2
|-
| b0.011 (3)||BL||BX||EBX||RBX||MM3||XMM3||YMM3||DS||CR3||DR3
|-
| b0.100 (4)||AH, SPL<span style="vertical-align: super">[[#Table2Note1|1]]</span>||SP||ESP||RSP||MM4||XMM4||YMM4||FS||CR4||DR4
|-
| b0.101 (5)||CH, BPL<span style="vertical-align: super">[[#Table2Note1|1]]</span>||BP||EBP||RBP||MM5||XMM5||YMM5||GS||CR5||DR5
|-
| b0.110 (6)||DH, SIL<span style="vertical-align: super">[[#Table2Note1|1]]</span>||SI||ESI||RSI||MM6||XMM6||YMM6||invalid||CR6||DR6
|-
| b0.111 (7)||BH, DIL<span style="vertical-align: super">[[#Table2Note1|1]]</span>||DI||EDI||RDI||MM7||XMM7||YMM7||invalid||CR7||DR7
|-
| b1.000 (8)||R8L||R8W||R8D||R8||MM0||XMM8||YMM8||ES||CR8||DR8
|-
| b1.001 (9)||R9L||R9W||R9D||R9||MM1||XMM9||YMM9||CS||CR9||DR9
|-
| b1.010 (10)||R10L||R10W||R10D||R10||MM2||XMM10||YMM10||SS||CR10||DR10
|-
| b1.011 (11)||R11L||R11W||R11D||R11||MM3||XMM11||YMM11||DS||CR11||DR11
|-
| b1.100 (12)||R12L||R12W||R12D||R12||MM4||XMM12||YMM12||FS||CR12||DR12
|-
| b1.101 (13)||R13L||R13W||R13D||R13||MM5||XMM13||YMM13||GS||CR13||DR13
|-
| b1.110 (14)||R14L||R14W||R14D||R14||MM6||XMM14||YMM14||invalid||CR14||DR14
|-
| b1.111 (15)||R15L||R15W||R15D||R15||MM7||XMM15||YMM15||invalid||CR15||DR15
|}
<small id="Table2Note1">1: When any REX prefix is used, SPL, BPL, SIL and DIL are used. Otherwise, without any REX prefix AH, CH, DH and BH are used.</small>
==== 16-bit addressing ====
|-
! 00
| style="background-color: white" |[BX] +[ SI]
| style="background-color: white" |[BX] +[ DI]
| style="background-color: white" |[BP] +[ SI]
| style="background-color: white" |[BP] +[ DI]
| style="background-color: white" |[SI]
| style="background-color: white" |[DI]
| style="background-color: white" |[disp16]
| style="background-color: white" |[BX]
|-
! 01
| style="background-color: white" |[BX] +[ SI] + disp8]
| style="background-color: white" |[BX] +[ DI] + disp8]
| style="background-color: white" |[BP] +[ SI] + disp8]
| style="background-color: white" |[BP] +[ DI] + disp8]
| style="background-color: white" |[SI] + disp8]
| style="background-color: white" |[DI] + disp8]
| style="background-color: white" |[BP] + disp8]
| style="background-color: white" |[BX] + disp8]
|-
! 10
| style="background-color: white" |[BX] +[ SI] + disp16]
| style="background-color: white" |[BX] +[ DI] + disp16]
| style="background-color: white" |[BP] +[ SI] + disp16]
| style="background-color: white" |[BP] +[ DI] + disp16]
| style="background-color: white" |[SI] + disp16]
| style="background-color: white" |[DI] + disp16]
| style="background-color: white" |[BP] + disp16]
| style="background-color: white" |[BX] + disp16]
|-
! 11
! 00
| style="background-color: white" colspan="4"|[r/m]
| style="background-color: white" |[[[#32-bit SIB byte|SIB]]]
| style="background-color: white" |[ #91;[[#RIP.2FEIP-relative_addressing|RIP/EIP]]]<span style="vertical-align: super">[[#Table5Note1Table8Note1|1]],[[#Table5Note2Table8Note2|2]]</span> + disp32]
| style="background-color: white" colspan="6"|[r/m]
| style="background-color: white" |[[[#32-bit SIB byte|SIB]]]
| style="background-color: white" |[ #91;[[#RIP.2FEIP-relative_addressing|RIP/EIP]]]<span style="vertical-align: super">[[#Table5Note1Table8Note1|1]],[[#Table5Note2Table8Note2|2]]</span> + disp32]
| style="background-color: white" colspan="2"|[r/m]
|-
! 01
| style="background-color: white" colspan="4"|[r/m] + disp8]
| style="background-color: white" |[[[#32-bit SIB byte|SIB]] + disp8]
| style="background-color: white" colspan="7"|[r/m] + disp8]
| style="background-color: white" |[[[#32-bit SIB byte|SIB]] + disp8]
| style="background-color: white" colspan="3"|[r/m] + disp8]
|-
! 10
| style="background-color: white" colspan="4"|[r/m] + disp32]
| style="background-color: white" |[[[#32-bit SIB byte|SIB]] + disp32]
| style="background-color: white" colspan="7"|[r/m] + disp32]
| style="background-color: white" |[[[#32-bit SIB byte|SIB]] + disp32]
| style="background-color: white" colspan="3"|[r/m] + disp32]
|-
! 11
|}
</div>
<small id="Table5Note1Table8Note1">1: In protected/compatibility mode, this is just ''disp32'', but in long mode this is ''[RIP]+disp32'' (for 64-bit addresses) or ''[EIP]+disp32'' (for 32-bit addresses, i.e. with address-size override prefix, [http://objectmix.com/asm-x86-asm-370/69055-effect-address-size-prefix-rip-relative-addressing.html see here]).</small><br />
<small id="Table5Note2Table8Note2">2: In long mode, to encode ''disp32'' as in protected/compatibility mode, use the SIB byte.</small>
===== RIP/EIP-relative addressing =====
Addressing in x86-64 can be relative to the current instruction pointer value. This is indicated with the ''RIP'' (64-bit) and ''EIP'' (32-bit) instruction pointer registers, which are not otherwise exposed to the program and may not exist physically. RIP-relative addressing allows object files to be location independent.
=== SIB ===
+---+---+---+---+---+---+---+---+
</pre>
{| {{wikitable|background-color: white}}
!style="background-color:#f9f9f9;"| Field
! Field
!style="background-color:#f9f9f9;"| Length
! Length
!style="background-color:#f9f9f9;"| Description
|-
!style="background-color:#f9f9f9; text-align: left; vertical-align: top;"|SIB.scale
| SIB.scale ||2 bits||This field indicates the scaling factor of SIB.index, where ''s'' (as used in the tables) equals 2<span style="vertical-align: super;">SIB.scale</span>.
|style="vertical-align: top;"|2 bits||This field indicates the scaling factor of SIB.index, where ''s'' (as used in the tables) equals 2<span style="vertical-align: super;">SIB.scale</span>.
{| {{wikitable}}
! SIB.scale
|}
|-
!style="background-color:#f9f9f9; text-align: left; vertical-align: top;"|SIB.index
| SIB.index||3 bits||The index register to use. See [[#Registers|Registers]] for the values to use for each of the registers. The REX.X, VEX.~X or XOP.~X field can extend this field with 1 most-significant bit to 4 bits total.
|style="vertical-align: top;"|3 bits||The index register to use. See [[#Registers|Registers]] for the values to use for each of the registers. The REX.X, VEX.~X or XOP.~X field can extend this field with 1 most-significant bit to 4 bits total.
|-
!style="background-color:#f9f9f9; text-align: left; vertical-align: top;"|SIB.base
| SIB.base||3 bits||The base register to use. See [[#Registers|Registers]] for the values to use for each of the registers. The REX.B, VEX.~B or XOP.~B field can extend this field with 1 most-significant bit to 4 bits total.
|style="vertical-align: top;"|3 bits||The base register to use. See [[#Registers|Registers]] for the values to use for each of the registers. The REX.B, VEX.~B or XOP.~B field can extend this field with 1 most-significant bit to 4 bits total.
|}
==== 32/64-bit addressing ====
The meaning of the SIB byte while using 32 or 64-bit addressing is as follows. The ModR/M byte's ''Mod'' field and the SIB byte's ''index'' field are used vertically, the SIB byte's ''base'' field and REX/VEX/XOP.B bit horizontally. The ''s'' is the [[#SIBScaleSIB|scaling factor]]. ''B.Base'', ''X.Index'' and ''Mod'' are in binary.
<div style="font-size: 70%; text-align: center">
{| {{wikitable}}
! 0.011<br />BX
! 0.100<br />SP
! 0.101<span style="vertical-align: super">[[#Table5Note1Table10Note1|1]]</span><br />BP
! 0.110<br />SI
! 0.111<br />DI
! 1.011<br />R11
! 1.100<br />R12
! 1.101<span style="vertical-align: super">[[#Table5Note1Table10Note1|1]]</span><br />R13
! 1.110<br />R14
! 1.111<br />R15
|-
! rowspan="16" | 00 !! style="text-align: left;" | 0.000 AX
| style="background-color: white" rowspan="4" colspan="5"|[base] + ([index] * s)]
| style="background-color: white" rowspan="4"|([(index] * s)<br />+ disp32]
| style="background-color: white" rowspan="4" colspan="7" |[base] + ([index] * s)]
| style="background-color: white" rowspan="4"|([(index] * s)<br />+ disp32]
| style="background-color: white" rowspan="4" colspan="2"|[base] + ([index] * s)]
|-
! style="text-align: left;" | 0.001 CX
! style="text-align: left;" | 0.011 BX
|-
! style="text-align: left;" | 0.100<span style="vertical-align: super">[[#Table5Note2Table10Note2|2]]</span> SP
| style="background-color: white" colspan="5"|[base]
| style="background-color: white"| [disp32]
| style="background-color: white" colspan="7"|[base]
| style="background-color: white"| [disp32]
| style="background-color: white" colspan="2"|[base]
|-
! style="text-align: left;" | 0.101 BP
| style="background-color: white" rowspan="11" colspan="5"|[base] + ([index] * s)]
| style="background-color: white" rowspan="11"|([(index] * s)<br />+ disp32]
| style="background-color: white" rowspan="11" colspan="7"|[base] + ([index] * s)]
| style="background-color: white" rowspan="11"|([(index] * s)<br />+ disp32]
| style="background-color: white" rowspan="11" colspan="2"|[base] + ([index] * s)]
|-
! style="text-align: left;" | 0.110 SI
|-
! rowspan="16" | 01 !! style="text-align: left;" | 0.000 AX
| style="background-color: white" rowspan="4" colspan="16"|[base] + ([index] * s) + disp8]
|-
! style="text-align: left;" | 0.001 CX
! style="text-align: left;" | 0.011 BX
|-
! style="text-align: left;" | 0.100<span style="vertical-align: super">[[#Table5Note2Table10Note2|2]]</span> SP
| style="background-color: white" colspan="16"|[base] + disp8]
|-
! style="text-align: left;" | 0.101 BP
| style="background-color: white" rowspan="11" colspan="16"|[base] + ([index] * s) + disp8]
|-
! style="text-align: left;" | 0.110 SI
|-
! rowspan="16" | 10 !! style="text-align: left;" | 0.000 AX
| style="background-color: white" rowspan="4" colspan="16"|[base] + ([index] * s) + disp32]
|-
! style="text-align: left;" | 0.001 CX
! style="text-align: left;" | 0.011 BX
|-
! style="text-align: left;" | 0.100<span style="vertical-align: super">[[#Table5Note2Table10Note2|2]]</span> SP
| style="background-color: white" colspan="16"|[base] + disp32]
|-
! style="text-align: left;" | 0.101 BP
| style="background-color: white" rowspan="11" colspan="16"|[base] + ([index] * s) + disp32]
|-
! style="text-align: left;" | 0.110 SI
|}
</div>
<small id="TableXNote1Table10Note1">1: No base register is encoded.</small><br />
<small id="TableXNote2Table10Note2">2: No index register is encoded.</small>
== Addressing modesDisplacement ==
A displacement value is a 1, 2, 4, or 8 byte offset added to the calculated address. When an 8 byte displacement is used, no immediate operand is encoded.
=== 8-bit addressing ===
Many instructions have a variant that allows the use of 8-bit register operands, and this requires no operand-size prefix. The x86-64 processors have no way to specify 8-bit addresses. These are the meanings of the ''Mod'' (vertically), ''R/M'' (horizontally) bits and REX prefix for 8-bit register operands:
{| {{wikitable}}
! !! colspan="8" | No REX prefix
|-
! Mod !! R/M=b000 !! b001 !! b010 !! b011 !! b100 !! b101 !! b110 !! b111
|-
! b00
| colspan="8" rowspan="3" style="text-align: center; vertical-align: middle" | N/A
|-
! b01
|-
! b10
|-
! b11
|AL||CL||DL||BL||AH||CH||DH||BH
|-
| colspan="9" style="background-color: white; border-bottom: solid 2px black; border-top: solid 2px black;" |
|-
! !! colspan="8" | REX.B = 0
|-
! Mod !! R/M=b000 !! b001 !! b010 !! b011 !! b100 !! b101 !! b110 !! b111
|-
! b00
| colspan="8" rowspan="3" style="text-align: center; vertical-align: middle" | N/A
|-
! b01
|-
! b10
|-
! b11
|AL||CL||DL||BL||BPL||SPL||SIL||DIL
|-
| colspan="9" style="background-color: white; border-bottom: solid 2px black; border-top: solid 2px black;" |
|-
! !! colspan="8" | REX.B = 1
|-
! Mod !! R/M=b000 !! b001 !! b010 !! b011 !! b100 !! b101 !! b110 !! b111
|-
! b00
| colspan="8" rowspan="3" style="text-align: center; vertical-align: middle" | N/A
|-
! b01
|-
! b10
|-
! b11
|R8L||R9L||R10L||R11L||R12L||R13L||R14L||R15L
|}
=== 16-bit addressing ===
In ''Long processing mode'' there is no way to specify 16-bit addresses. These are the meanings of the ''Mod'' (vertically), ''R/M'' (horizontally) bits and REX prefix for [[#Operand-size and address-size override prefix|16-bit addressing]]: (The SIB-byte is not used in 16-bit addressing.)
{| {{wikitable}}
! !! colspan="8" | REX.B = 0 or no REX prefix
|-
! Mod !! R/M=b000 !! b001 !! b010 !! b011 !! b100 !! b101 !! b110 !! b111
|-
! b00
|[BX+SI]||[BX+DI]||[BP+SI]||[BP+DI]||[SI]||[DI]||disp16||[BX]
|-
! b01
|[BX+SI]+disp8||[BX+DI]+disp8||[BP+SI]+disp8||[BP+DI]+disp8||[SI]+disp8||[DI]+disp8||[BP]+disp8||[BX]+disp8
|-
! b10
|[BX+SI]+disp16||[BX+DI]+disp16||[BP+SI]+disp16||[BP+DI]+disp16||[SI]+disp16||[DI]+disp16||[BP]+disp16||[BX]+disp16
|-
! b11
|AL||CL||DL||BL||AH||CH||DH||BH
|-
| colspan="9" style="background-color: white; border-bottom: solid 2px black; border-top: solid 2px black;" |
|-
! !! colspan="8" | REX.B = 1
|-
! Mod !! R/M=b000 !! b001 !! b010 !! b011 !! b100 !! b101 !! b110 !! b111
|-
! b00
| colspan="8" rowspan="3" style="text-align: center; vertical-align: middle" | N/A
|-
! b01
|-
! b10
|-
! b11
|R8W||R9W||R10W||R11W||R12W||R13W||R14W||R15W
|}
=== 32-bit addressing ===
These are the meanings of the ''Mod'' (vertically) and ''R/M'' (horizontally) bits for [[#Operand-size and address-size override prefix|32-bit addressing]]:
{| {{wikitable}}
! !! colspan="8" | REX.B = 0 or no REX prefix
|-
! Mod !! R/M=b000 !! b001 !! b010 !! b011 !! b100 !! b101 !! b110 !! b111
|-
! b00
|[EAX]||[ECX]||[EDX]||[EBX]||[[#32-bit SIB byte|SIB]]||([[#RIP.2FEIP-relative_addressing|EIP]]+)disp32<span style="vertical-align: super">[[#Table5Note1|1]],[[#Table5Note2|2]]</span>||[ESI]||[EDI]
|-
! b01
|[EAX]+disp8||[ECX]+disp8||[EDX]+disp8||[EBX]+disp8||[[#32-bit SIB byte|SIB]]+disp8||[EBP]+disp8||[ESI]+disp8||[EDI]+disp8
|-
! b10
|[EAX]+disp32||[ECX]+disp32||[EDX]+disp32||[EBX]+disp32||[[#32-bit SIB byte|SIB]]+disp32||[EBP]+disp32||[ESI]+disp32||[EDI]+disp32
|-
! b11
|EAX, MM0, XMM0||ECX, MM1, XMM1||EDX, MM2, XMM2||EBX, MM3, XMM3||ESP, MM4, XMM4||EBP, MM5, XMM5||ESI, MM6, XMM6||EDI, MM7, XMM7
|-
| colspan="9" style="background-color: white; border-top: solid 2px black; border-bottom: solid 2px black; border-left: none; border-right: none;" |
|-
! !! colspan="8" | REX.B = 1
|-
! Mod !! R/M=b000 !! b001 !! b010 !! b011 !! b100 !! b101 !! b110 !! b111
|-
! b00
|[R8D]||[R9D]||[R10D]||[R11D]||[R12D]||[R13D]||[R14D]||[R15D]
|-
! b01
|[R8D]+disp8||[R9D]+disp8||[R10D]+disp8||[R11D]+disp8||[R12D]+disp8||[R13D]+disp8||[R14D]+disp8||[R15D]+disp8
|-
! b10
|[R8D]+disp32||[R9D]+disp32||[R10D]+disp32||[R11D]+disp32||[R12D]+disp32||[R13D]+disp32||[R14D]+disp32||[R15D]+disp32
|-
! b11
|R8D, MM0, XMM8||R9D, MM1, XMM9||R10D, MM2, XMM10||R11D, MM3, XMM11||R12D, MM4, XMM12||R13D, MM5, XMM13||R14D, MM6, XMM14||R15D, MM7, XMM15
|}
<small id="Table5Note1">1: In protected/compatibility mode, this is just ''disp32'', but in long mode this is ''EIP+disp32''.</small><br />
<small id="Table5Note2">2: In long mode, to encode ''disp32'' as in protected/compatibility mode, use the SIB byte.</small>
==== 32-bit SIB byte ====
The meaning of the SIB byte while using 32-bit addressing is as follows. The ModR/M byte's ''Mod'' field and the SIB byte's ''index'' field are used vertically, the SIB byte's ''base'' field horizontally. The ''s'' is the [[#SIBScale|scaling factor]].
<div style="font-size: 70%">
{| {{wikitable}}
! Mod
! Index
! Base=b000
! b001
! b010
! b011
! b100
! b101
! b110
! b111
|-
! rowspan="8" | b00!!b000
|[EAX] + ([EAX] * s)||[ECX] + ([EAX] * s)||[EDX] + ([EAX] * s)||[EBX] + ([EAX] * s)||[ESP] + ([EAX] * s)||([EAX] * s) + disp32||[ESI] + ([EAX] * s)||[EDI] + ([EAX] * s)
|-
! b001
|[EAX] + ([ECX] * s)||[ECX] + ([ECX] * s)||[EDX] + ([ECX] * s)||[EBX] + ([ECX] * s)||[ESP] + ([ECX] * s)||([ECX] * s) + disp32||[ESI] + ([ECX] * s)||[EDI] + ([ECX] * s)
|-
! b010
|[EAX] + ([EDX] * s)||[ECX] + ([EDX] * s)||[EDX] + ([EDX] * s)||[EBX] + ([EDX] * s)||[ESP] + ([EDX] * s)||([EDX] * s) + disp32||[ESI] + ([EDX] * s)||[EDI] + ([EDX] * s)
|-
! b011
|[EAX] + ([EBX] * s)||[ECX] + ([EBX] * s)||[EDX] + ([EBX] * s)||[EBX] + ([EBX] * s)||[ESP] + ([EBX] * s)||([EBX] * s) + disp32||[ESI] + ([EBX] * s)||[EDI] + ([EBX] * s)
|-
! b100
|[EAX]||[ECX]||[EDX]||[EBX]||[ESP]||disp32||[ESI]||[EDI]
|-
! b101
|[EAX] + ([EBP] * s)||[ECX] + ([EBP] * s)||[EDX] + ([EBP] * s)||[EBX] + ([EBP] * s)||[ESP] + ([EBP] * s)||([EBP] * s) + disp32||[ESI] + ([EBP] * s)||[EDI] + ([EBP] * s)
|-
! b110
|[EAX] + ([ESI] * s)||[ECX] + ([ESI] * s)||[EDX] + ([ESI] * s)||[EBX] + ([ESI] * s)||[ESP] + ([ESI] * s)||([ESI] * s) + disp32||[ESI] + ([ESI] * s)||[EDI] + ([ESI] * s)
|-
! b111
|[EAX] + ([EDI] * s)||[ECX] + ([EDI] * s)||[EDX] + ([EDI] * s)||[EBX] + ([EDI] * s)||[ESP] + ([EDI] * s)||([EDI] * s) + disp32||[ESI] + ([EDI] * s)||[EDI] + ([EDI] * s)
|-
| colspan="10" style="background-color: white; border-top: solid 2px black; border-bottom: solid 2px black; border-left: none; border-right: none;" |
|-
! rowspan="8" | b01!!b000
|[EAX] + ([EAX] * s) + disp8||[ECX] + ([EAX] * s) + disp8||[EDX] + ([EAX] * s) + disp8||[EBX] + ([EAX] * s) + disp8||[ESP] + ([EAX] * s) + disp8||[EBP] + ([EAX] * s) + disp8||[ESI] + ([EAX] * s) + disp8||[EDI] + ([EAX] * s) + disp8
|-
! b001
|[EAX] + ([ECX] * s) + disp8||[ECX] + ([ECX] * s) + disp8||[EDX] + ([ECX] * s) + disp8||[EBX] + ([ECX] * s) + disp8||[ESP] + ([ECX] * s) + disp8||[EBP] + ([ECX] * s) + disp8||[ESI] + ([ECX] * s) + disp8||[EDI] + ([ECX] * s) + disp8
|-
! b010
|[EAX] + ([EDX] * s) + disp8||[ECX] + ([EDX] * s) + disp8||[EDX] + ([EDX] * s) + disp8||[EBX] + ([EDX] * s) + disp8||[ESP] + ([EDX] * s) + disp8||[EBP] + ([EDX] * s) + disp8||[ESI] + ([EDX] * s) + disp8||[EDI] + ([EDX] * s) + disp8
|-
! b011
|[EAX] + ([EBX] * s) + disp8||[ECX] + ([EBX] * s) + disp8||[EDX] + ([EBX] * s) + disp8||[EBX] + ([EBX] * s) + disp8||[ESP] + ([EBX] * s) + disp8||[EBP] + ([EBX] * s) + disp8||[ESI] + ([EBX] * s) + disp8||[EDI] + ([EBX] * s) + disp8
|-
! b100
|[EAX] + disp8||[ECX] + disp8||[EDX] + disp8||[EBX] + disp8||[ESP] + disp8||[EBP] + disp8||[ESI] + disp8||[EDI] + disp8
|-
! b101
|[EAX] + ([EBP] * s) + disp8||[ECX] + ([EBP] * s) + disp8||[EDX] + ([EBP] * s) + disp8||[EBX] + ([EBP] * s) + disp8||[ESP] + ([EBP] * s) + disp8||[EBP] + ([EBP] * s) + disp8||[ESI] + ([EBP] * s) + disp8||[EDI] + ([EBP] * s) + disp8
|-
! b110
|[EAX] + ([ESI] * s) + disp8||[ECX] + ([ESI] * s) + disp8||[EDX] + ([ESI] * s) + disp8||[EBX] + ([ESI] * s) + disp8||[ESP] + ([ESI] * s) + disp8||[EBP] + ([ESI] * s) + disp8||[ESI] + ([ESI] * s) + disp8||[EDI] + ([ESI] * s) + disp8
|-
! b111
|[EAX] + ([EDI] * s) + disp8||[ECX] + ([EDI] * s) + disp8||[EDX] + ([EDI] * s) + disp8||[EBX] + ([EDI] * s) + disp8||[ESP] + ([EDI] * s) + disp8||[EBP] + ([EDI] * s) + disp8||[ESI] + ([EDI] * s) + disp8||[EDI] + ([EDI] * s) + disp8
|-
| colspan="10" style="background-color: white; border-top: solid 2px black; border-bottom: solid 2px black; border-left: none; border-right: none;" |
|-
! rowspan="8" | b10!!b000
|[EAX] + ([EAX] * s) + disp32||[ECX] + ([EAX] * s) + disp32||[EDX] + ([EAX] * s) + disp32||[EBX] + ([EAX] * s) + disp32||[ESP] + ([EAX] * s) + disp32||[EBP] + ([EAX] * s) + disp32||[ESI] + ([EAX] * s) + disp32||[EDI] + ([EAX] * s) + disp32
|-
! b001
|[EAX] + ([ECX] * s) + disp32||[ECX] + ([ECX] * s) + disp32||[EDX] + ([ECX] * s) + disp32||[EBX] + ([ECX] * s) + disp32||[ESP] + ([ECX] * s) + disp32||[EBP] + ([ECX] * s) + disp32||[ESI] + ([ECX] * s) + disp32||[EDI] + ([ECX] * s) + disp32
|-
! b010
|[EAX] + ([EDX] * s) + disp32||[ECX] + ([EDX] * s) + disp32||[EDX] + ([EDX] * s) + disp32||[EBX] + ([EDX] * s) + disp32||[ESP] + ([EDX] * s) + disp32||[EBP] + ([EDX] * s) + disp32||[ESI] + ([EDX] * s) + disp32||[EDI] + ([EDX] * s) + disp32
|-
! b011
|[EAX] + ([EBX] * s) + disp32||[ECX] + ([EBX] * s) + disp32||[EDX] + ([EBX] * s) + disp32||[EBX] + ([EBX] * s) + disp32||[ESP] + ([EBX] * s) + disp32||[EBP] + ([EBX] * s) + disp32||[ESI] + ([EBX] * s) + disp32||[EDI] + ([EBX] * s) + disp32
|-
! b100
|[EAX] + disp32||[ECX] + disp32||[EDX] + disp32||[EBX] + disp32||[ESP] + disp32||[EBP] + disp32||[ESI] + disp32||[EDI] + disp32
|-
! b101
|[EAX] + ([EBP] * s) + disp32||[ECX] + ([EBP] * s) + disp32||[EDX] + ([EBP] * s) + disp32||[EBX] + ([EBP] * s) + disp32||[ESP] + ([EBP] * s) + disp32||[EBP] + ([EBP] * s) + disp32||[ESI] + ([EBP] * s) + disp32||[EDI] + ([EBP] * s) + disp32
|-
! b110
|[EAX] + ([ESI] * s) + disp32||[ECX] + ([ESI] * s) + disp32||[EDX] + ([ESI] * s) + disp32||[EBX] + ([ESI] * s) + disp32||[ESP] + ([ESI] * s) + disp32||[EBP] + ([ESI] * s) + disp32||[ESI] + ([ESI] * s) + disp32||[EDI] + ([ESI] * s) + disp32
|-
! b111
|[EAX] + ([EDI] * s) + disp32||[ECX] + ([EDI] * s) + disp32||[EDX] + ([EDI] * s) + disp32||[EBX] + ([EDI] * s) + disp32||[ESP] + ([EDI] * s) + disp32||[EBP] + ([EDI] * s) + disp32||[ESI] + ([EDI] * s) + disp32||[EDI] + ([EDI] * s) + disp32
|}
</div>
=== 64-bit addressing ===
These are the meanings of the ''Mod'' (vertically), ''R/M'' (horizontally) and ''REX.B'' (also horizontally) bits for [[#Operand-size and address-size override prefix|64-bit addressing]]:
{| {{wikitable}}
! !! colspan="8" | REX.B = 0 or no REX prefix
|-
! Mod !! R/M=b000 !! b001 !! b010 !! b011 !! b100 !! b101 !! b110 !! b111
|-
! b00
|[RAX]||[RCX]||[RDX]||[RBX]||[[#32-bit SIB byte|SIB]]||[[#RIP.2FEIP-relative_addressing|RIP]]+disp32<span style="vertical-align: super">[[#Table6Note1|1]]</span>||[RSI]||[RDI]
|-
! b01
|[RAX]+disp8||[RCX]+disp8||[RDX]+disp8||[RBX]+disp8||[[#32-bit SIB byte|SIB]]+disp8||[RBP]+disp8||[RSI]+disp8||[RDI]+disp8
|-
! b10
|[RAX]+disp32||[RCX]+disp32||[RDX]+disp32||[RBX]+disp32||[[#32-bit SIB byte|SIB]]+disp32||[RBP]+disp32||[RSI]+disp32||[RDI]+disp32
|-
! b11
|RAX, MM0, XMM0||RCX, MM1, XMM1||RDX, MM2, XMM2||RBX, MM3, XMM3||RSP, MM4, XMM4||RBP, MM5, XMM5||RSI, MM6, XMM6||RDI, MM7, XMM7
|-
| colspan="9" style="background-color: white; border-top: solid 2px black; border-bottom: solid 2px black; border-left: none; border-right: none;" |
|-
! !! colspan="8" | REX.B = 1
|-
! Mod !! R/M=b000 !! b001 !! b010 !! b011 !! b100 !! b101 !! b110 !! b111
|-
! b00
|[R8]||[R9]||[R10]||[R11]||[R12]||[R13]||[R14]||[R15]
|-
! b01
|[R8]+disp8||[R9]+disp8||[R10]+disp8||[R11]+disp8||[R12]+disp8||[R13]+disp8||[R14]+disp8||[R15]+disp8
|-
! b10
|[R8]+disp32||[R9]+disp32||[R10]+disp32||[R11]+disp32||[R12]+disp32||[R13]+disp32||[R14]+disp32||[R15]+disp32
|-
! b11
|R8, MM0, XMM8||R9, MM1, XMM9||R10, MM2, XMM10||R11, MM3, XMM11||R12, MM4, XMM12||R13, MM5, XMM13||R14, MM6, XMM14||R15, MM7, XMM15
|}
<small id="Table6Note1">1: To encode ''disp32'' as in protected/compatibility mode, use the SIB byte.</small>
==== SIB byte ====
The meaning of the SIB byte in 32-bit or 64-bit addressing is as follows. The ''MODRM.mod'' field, the ''SIB.index'' field and ''REX.X''/''VEX.~X''/''XOP.~X'' bits (denoted as ''X'') are used vertically, the ''SIB.base'' field and ''REX.B''/''VEX.~B''/''XOP.~B'' bits (denoted as ''B'') horizontally. The ''s'' is the [[#SIBScale|scaling factor]].
<div style="font-size: 70%">
{| {{wikitable}}
! !! !! !! colspan="8" | B = 0
|-
! Mod
! X
! Index
! Base=b000
! b001
! b010
! b011
! b100
! b101
! b110
! b111
|-
! rowspan="16" | b00 !! 0 !! b000
|[_AX] + ([_AX] * s)||[_CX] + ([_AX] * s)||[_DX] + ([_AX] * s)||[_BX] + ([_AX] * s)||[_SP] + ([_AX] * s)||([_AX] * s) + disp32||[_SI] + ([_AX] * s)||[_DI] + ([_AX] * s)
|-
! 0 !! b001
|[_AX] + ([_CX] * s)||[_CX] + ([_CX] * s)||[_DX] + ([_CX] * s)||[_BX] + ([_CX] * s)||[_SP] + ([_CX] * s)||([_CX] * s) + disp32||[_SI] + ([_CX] * s)||[_DI] + ([_CX] * s)
|-
! 0 !! b010
|[_AX] + ([_DX] * s)||[_CX] + ([_DX] * s)||[_DX] + ([_DX] * s)||[_BX] + ([_DX] * s)||[_SP] + ([_DX] * s)||([_DX] * s) + disp32||[_SI] + ([_DX] * s)||[_DI] + ([_DX] * s)
|-
! 0 !! b011
|[_AX] + ([_BX] * s)||[_CX] + ([_BX] * s)||[_DX] + ([_BX] * s)||[_BX] + ([_BX] * s)||[_SP] + ([_BX] * s)||([_BX] * s) + disp32||[_SI] + ([_BX] * s)||[_DI] + ([_BX] * s)
|-
! 0 !! b100
|[_AX]||[_CX]||[_DX]||[_BX]||[_SP]||disp32||[_SI]||[_DI]
|-
! 0 !! b101
|[_AX] + ([_BP] * s)||[_CX] + ([_BP] * s)||[_DX] + ([_BP] * s)||[_BX] + ([_BP] * s)||[_SP] + ([_BP] * s)||([_BP] * s) + disp32||[_SI] + ([_BP] * s)||[_DI] + ([_BP] * s)
|-
! 0 !! b110
|[_AX] + ([_SI] * s)||[_CX] + ([_SI] * s)||[_DX] + ([_SI] * s)||[_BX] + ([_SI] * s)||[_SP] + ([_SI] * s)||([_SI] * s) + disp32||[_SI] + ([_SI] * s)||[_DI] + ([_SI] * s)
|-
! 0 !! b111
|[_AX] + ([_DI] * s)||[_CX] + ([_DI] * s)||[_DX] + ([_DI] * s)||[_BX] + ([_DI] * s)||[_SP] + ([_DI] * s)||([_DI] * s) + disp32||[_SI] + ([_DI] * s)||[_DI] + ([_DI] * s)
|-
! 1 !! b000
|[_AX] + ([R8_] * s)||[_CX] + ([R8_] * s)||[_DX] + ([R8_] * s)||[_BX] + ([R8_] * s)||[_SP] + ([R8_] * s)||([R8_] * s) + disp32||[_SI] + ([R8_] * s)||[_DI] + ([R8_] * s)
|-
! 1 !! b001
|[_AX] + ([R9_] * s)||[_CX] + ([R9_] * s)||[_DX] + ([R9_] * s)||[_BX] + ([R9_] * s)||[_SP] + ([R9_] * s)||([R9_] * s) + disp32||[_SI] + ([R9_] * s)||[_DI] + ([R9_] * s)
|-
! 1 !! b010
|[_AX] + ([R10_] * s)||[_CX] + ([R10_] * s)||[_DX] + ([R10_] * s)||[_BX] + ([R10_] * s)||[_SP] + ([R10_] * s)||([R10_] * s) + disp32||[_SI] + ([R10_] * s)||[_DI] + ([R10_] * s)
|-
! 1 !! b011
|[_AX] + ([R11_] * s)||[_CX] + ([R11_] * s)||[_DX] + ([R11_] * s)||[_BX] + ([R11_] * s)||[_SP] + ([R11_] * s)||([R11_] * s) + disp32||[_SI] + ([R11_] * s)||[_DI] + ([R11_] * s)
|-
! 1 !! b100
|[_AX] + ([R12_] * s)||[_CX] + ([R12_] * s)||[_DX] + ([R12_] * s)||[_BX] + ([R12_] * s)||[_SP] + ([R12_] * s)||disp32||[_SI] + ([R12_] * s)||[_DI] + ([R12_] * s)
|-
! 1 !! b101
|[_AX] + ([R13_] * s)||[_CX] + ([R13_] * s)||[_DX] + ([R13_] * s)||[_BX] + ([R13_] * s)||[_SP] + ([R13_] * s)||([R13_] * s) + disp32||[_SI] + ([R13_] * s)||[_DI] + ([R13_] * s)
|-
! 1 !! b110
|[_AX] + ([R14_] * s)||[_CX] + ([R14_] * s)||[_DX] + ([R14_] * s)||[_BX] + ([R14_] * s)||[_SP] + ([R14_] * s)||([R14_] * s) + disp32||[_SI] + ([R14_] * s)||[_DI] + ([R14_] * s)
|-
! 1 !! b111
|[_AX] + ([R15_] * s)||[_CX] + ([R15_] * s)||[_DX] + ([R15_] * s)||[_BX] + ([R15_] * s)||[_SP] + ([R15_] * s)||([R15_] * s) + disp32||[_SI] + ([R15_] * s)||[_DI] + ([R15_] * s)
|-
| colspan="11" style="background-color: white; border-top: solid 2px black; border-bottom: solid 2px black; border-left: none; border-right: none;" |
|-
! !! !! !! colspan="8" | REX.B = 1
|-
! Mod
! X
! Index
! Base=b000
! b001
! b010
! b011
! b100
! b101
! b110
! b111
|-
! rowspan="16" | b00 !! 0 !! b000
|[R8_] + ([_AX] * s)||[R9_] + ([_AX] * s)||[R10_] + ([_AX] * s)||[R11_] + ([_AX] * s)||[R12_] + ([_AX] * s)||([_AX] * s) + disp32||[R14_] + ([_AX] * s)||[R15_] + ([_AX] * s)
|-
! 0 !! b001
|[R8_] + ([_CX] * s)||[R9_] + ([_CX] * s)||[R10_] + ([_CX] * s)||[R11_] + ([_CX] * s)||[R12_] + ([_CX] * s)||([_CX] * s) + disp32||[R14_] + ([_CX] * s)||[R15_] + ([_CX] * s)
|-
! 0 !! b010
|[R8_] + ([_DX] * s)||[R9_] + ([_DX] * s)||[R10_] + ([_DX] * s)||[R11_] + ([_DX] * s)||[R12_] + ([_DX] * s)||([_DX] * s) + disp32||[R14_] + ([_DX] * s)||[R15_] + ([_DX] * s)
|-
! 0 !! b011
|[R8_] + ([_BX] * s)||[R9_] + ([_BX] * s)||[R10_] + ([_BX] * s)||[R11_] + ([_BX] * s)||[R12_] + ([_BX] * s)||([_BX] * s) + disp32||[R14_] + ([_BX] * s)||[R15_] + ([_BX] * s)
|-
! 0 !! b100
|[R8_]||[R9_]||[R10_]||[R11_]||[R12_]||disp32||[R14_]||[R15_]
|-
! 0 !! b101
|[R8_] + ([_BP] * s)||[R9_] + ([_BP] * s)||[R10_] + ([_BP] * s)||[R11_] + ([_BP] * s)||[R12_] + ([_BP] * s)||([_BP] * s) + disp32||[R14_] + ([_BP] * s)||[R15_] + ([_BP] * s)
|-
! 0 !! b110
|[R8_] + ([_SI] * s)||[R9_] + ([_SI] * s)||[R10_] + ([_SI] * s)||[R11_] + ([_SI] * s)||[R12_] + ([_SI] * s)||([_SI] * s) + disp32||[R14_] + ([_SI] * s)||[R15_] + ([_SI] * s)
|-
! 0 !! b111
|[R8_] + ([_DI] * s)||[R9_] + ([_DI] * s)||[R10_] + ([_DI] * s)||[R11_] + ([_DI] * s)||[R12_] + ([_DI] * s)||([_DI] * s) + disp32||[R14_] + ([_DI] * s)||[R15_] + ([_DI] * s)
|-
! 1 !! b000
|[R8_] + ([R8_] * s)||[R9_] + ([R8_] * s)||[R10_] + ([R8_] * s)||[R11_] + ([R8_] * s)||[R12_] + ([R8_] * s)||([R8_] * s) + disp32||[R14_] + ([R8_] * s)||[R15_] + ([R8_] * s)
|-
! 1 !! b001
|[R8_] + ([R9_] * s)||[R9_] + ([R9_] * s)||[R10_] + ([R9_] * s)||[R11_] + ([R9_] * s)||[R12_] + ([R9_] * s)||([R9_] * s) + disp32||[R14_] + ([R9_] * s)||[R15_] + ([R9_] * s)
|-
! 1 !! b010
|[R8_] + ([R10_] * s)||[R9_] + ([R10_] * s)||[R10_] + ([R10_] * s)||[R11_] + ([R10_] * s)||[R12_] + ([R10_] * s)||([R10_] * s) + disp32||[R14_] + ([R10_] * s)||[R15_] + ([R10_] * s)
|-
! 1 !! b011
|[R8_] + ([R11_] * s)||[R9_] + ([R11_] * s)||[R10_] + ([R11_] * s)||[R11_] + ([R11_] * s)||[R12_] + ([R11_] * s)||([R11_] * s) + disp32||[R14_] + ([R11_] * s)||[R15_] + ([R11_] * s)
|-
! 1 !! b100
|[R8_] + ([R12_] * s)||[R9_] + ([R12_] * s)||[R10_] + ([R12_] * s)||[R11_] + ([R12_] * s)||[R12_] + ([R12_] * s)||disp32||[R14_] + ([R12_] * s)||[R15_] + ([R12_] * s)
|-
! 1 !! b101
|[R8_] + ([R13_] * s)||[R9_] + ([R13_] * s)||[R10_] + ([R13_] * s)||[R11_] + ([R13_] * s)||[R12_] + ([R13_] * s)||([R13_] * s) + disp32||[R14_] + ([R13_] * s)||[R15_] + ([R13_] * s)
|-
! 1 !! b110
|[R8_] + ([R14_] * s)||[R9_] + ([R14_] * s)||[R10_] + ([R14_] * s)||[R11_] + ([R14_] * s)||[R12_] + ([R14_] * s)||([R14_] * s) + disp32||[R14_] + ([R14_] * s)||[R15_] + ([R14_] * s)
|-
! 1 !! b111
|[R8_] + ([R15_] * s)||[R9_] + ([R15_] * s)||[R10_] + ([R15_] * s)||[R11_] + ([R15_] * s)||[R12_] + ([R15_] * s)||([R15_] * s) + disp32||[R14_] + ([R15_] * s)||[R15_] + ([R15_] * s)
|-
| colspan="11" style="background-color: white; border-top: solid 2px black; border-bottom: solid 2px black; border-left: none; border-right: none;" |
|-
! !! !! !! colspan="8" | REX.B = 0
|-
! Mod
! X
! Index
! Base=b000
! b001
! b010
! b011
! b100
! b101
! b110
! b111
|-
! rowspan="16" | b01 !! 0 !! b000
|[_AX] + ([_AX] * s) + disp8||[_CX] + ([_AX] * s) + disp8||[_DX] + ([_AX] * s) + disp8||[_BX] + ([_AX] * s) + disp8||[_SP] + ([_AX] * s) + disp8||[_BP] + ([_AX] * s) + disp8||[_SI] + ([_AX] * s) + disp8||[_DI] + ([_AX] * s) + disp8
|-
! 0 !! b001
|[_AX] + ([_CX] * s) + disp8||[_CX] + ([_CX] * s) + disp8||[_DX] + ([_CX] * s) + disp8||[_BX] + ([_CX] * s) + disp8||[_SP] + ([_CX] * s) + disp8||[_BP] + ([_CX] * s) + disp8||[_SI] + ([_CX] * s) + disp8||[_DI] + ([_CX] * s) + disp8
|-
! 0 !! b010
|[_AX] + ([_DX] * s) + disp8||[_CX] + ([_DX] * s) + disp8||[_DX] + ([_DX] * s) + disp8||[_BX] + ([_DX] * s) + disp8||[_SP] + ([_DX] * s) + disp8||[_BP] + ([_DX] * s) + disp8||[_SI] + ([_DX] * s) + disp8||[_DI] + ([_DX] * s) + disp8
|-
! 0 !! b011
|[_AX] + ([_BX] * s) + disp8||[_CX] + ([_BX] * s) + disp8||[_DX] + ([_BX] * s) + disp8||[_BX] + ([_BX] * s) + disp8||[_SP] + ([_BX] * s) + disp8||[_BP] + ([_BX] * s) + disp8||[_SI] + ([_BX] * s) + disp8||[_DI] + ([_BX] * s) + disp8
|-
! 0 !! b100
|[_AX] + disp8||[_CX] + disp8||[_DX] + disp8||[_BX] + disp8||[_SP] + disp8||[_BP] + disp8||[_SI] + disp8||[_DI] + disp8
|-
! 0 !! b101
|[_AX] + ([_BP] * s) + disp8||[_CX] + ([_BP] * s) + disp8||[_DX] + ([_BP] * s) + disp8||[_BX] + ([_BP] * s) + disp8||[_SP] + ([_BP] * s) + disp8||[_BP] + ([_BP] * s) + disp8||[_SI] + ([_BP] * s) + disp8||[_DI] + ([_BP] * s) + disp8
|-
! 0 !! b110
|[_AX] + ([_SI] * s) + disp8||[_CX] + ([_SI] * s) + disp8||[_DX] + ([_SI] * s) + disp8||[_BX] + ([_SI] * s) + disp8||[_SP] + ([_SI] * s) + disp8||[_BP] + ([_SI] * s) + disp8||[_SI] + ([_SI] * s) + disp8||[_DI] + ([_SI] * s) + disp8
|-
! 0 !! b111
|[_AX] + ([_DI] * s) + disp8||[_CX] + ([_DI] * s) + disp8||[_DX] + ([_DI] * s) + disp8||[_BX] + ([_DI] * s) + disp8||[_SP] + ([_DI] * s) + disp8||[_BP] + ([_DI] * s) + disp8||[_SI] + ([_DI] * s) + disp8||[_DI] + ([_DI] * s) + disp8
|-
! 1 !! b000
|[_AX] + ([R8_] * s) + disp8||[_CX] + ([R8_] * s) + disp8||[_DX] + ([R8_] * s) + disp8||[_BX] + ([R8_] * s) + disp8||[_SP] + ([R8_] * s) + disp8||[_BP] + ([R8_] * s) + disp8||[_SI] + ([R8_] * s) + disp8||[_DI] + ([R8_] * s) + disp8
|-
! 1 !! b001
|[_AX] + ([R9_] * s) + disp8||[_CX] + ([R9_] * s) + disp8||[_DX] + ([R9_] * s) + disp8||[_BX] + ([R9_] * s) + disp8||[_SP] + ([R9_] * s) + disp8||[_BP] + ([R9_] * s) + disp8||[_SI] + ([R9_] * s) + disp8||[_DI] + ([R9_] * s) + disp8
|-
! 1 !! b010
|[_AX] + ([R10_] * s) + disp8||[_CX] + ([R10_] * s) + disp8||[_DX] + ([R10_] * s) + disp8||[_BX] + ([R10_] * s) + disp8||[_SP] + ([R10_] * s) + disp8||[_BP] + ([R10_] * s) + disp8||[_SI] + ([R10_] * s) + disp8||[_DI] + ([R10_] * s) + disp8
|-
! 1 !! b011
|[_AX] + ([R11_] * s) + disp8||[_CX] + ([R11_] * s) + disp8||[_DX] + ([R11_] * s) + disp8||[_BX] + ([R11_] * s) + disp8||[_SP] + ([R11_] * s) + disp8||[_BP] + ([R11_] * s) + disp8||[_SI] + ([R11_] * s) + disp8||[_DI] + ([R11_] * s) + disp8
|-
! 1 !! b100
|[_AX] + ([R12_] * s) + disp8||[_CX] + ([R12_] * s) + disp8||[_DX] + ([R12_] * s) + disp8||[_BX] + ([R12_] * s) + disp8||[_SP] + ([R12_] * s) + disp8||[_BP] + ([R12_] * s) + disp8||[_SI] + ([R12_] * s) + disp8||[_DI] + ([R12_] * s) + disp8
|-
! 1 !! b101
|[_AX] + ([R13_] * s) + disp8||[_CX] + ([R13_] * s) + disp8||[_DX] + ([R13_] * s) + disp8||[_BX] + ([R13_] * s) + disp8||[_SP] + ([R13_] * s) + disp8||[_BP] + ([R13_] * s) + disp8||[_SI] + ([R13_] * s) + disp8||[_DI] + ([R13_] * s) + disp8
|-
! 1 !! b110
|[_AX] + ([R14_] * s) + disp8||[_CX] + ([R14_] * s) + disp8||[_DX] + ([R14_] * s) + disp8||[_BX] + ([R14_] * s) + disp8||[_SP] + ([R14_] * s) + disp8||[_BP] + ([R14_] * s) + disp8||[_SI] + ([R14_] * s) + disp8||[_DI] + ([R14_] * s) + disp8
|-
! 1 !! b111
|[_AX] + ([R15_] * s) + disp8||[_CX] + ([R15_] * s) + disp8||[_DX] + ([R15_] * s) + disp8||[_BX] + ([R15_] * s) + disp8||[_SP] + ([R15_] * s) + disp8||[_BP] + ([R15_] * s) + disp8||[_SI] + ([R15_] * s) + disp8||[_DI] + ([R15_] * s) + disp8
|-
| colspan="11" style="background-color: white; border-top: solid 2px black; border-bottom: solid 2px black; border-left: none; border-right: none;" |
|-
! !! !! !! colspan="8" | REX.B = 1
|-
! Mod
! X
! Index
! Base=b000
! b001
! b010
! b011
! b100
! b101
! b110
! b111
|-
! rowspan="16" | b01 !! 0 !! b000
|[R8_] + ([_AX] * s) + disp8||[R9_] + ([_AX] * s) + disp8||[R10_] + ([_AX] * s) + disp8||[R11_] + ([_AX] * s) + disp8||[R12_] + ([_AX] * s) + disp8||[R13_] + ([_AX] * s) + disp8||[R14_] + ([_AX] * s) + disp8||[R15_] + ([_AX] * s) + disp8
|-
! 0 !! b001
|[R8_] + ([_CX] * s) + disp8||[R9_] + ([_CX] * s) + disp8||[R10_] + ([_CX] * s) + disp8||[R11_] + ([_CX] * s) + disp8||[R12_] + ([_CX] * s) + disp8||[R13_] + ([_CX] * s) + disp8||[R14_] + ([_CX] * s) + disp8||[R15_] + ([_CX] * s) + disp8
|-
! 0 !! b010
|[R8_] + ([_DX] * s) + disp8||[R9_] + ([_DX] * s) + disp8||[R10_] + ([_DX] * s) + disp8||[R11_] + ([_DX] * s) + disp8||[R12_] + ([_DX] * s) + disp8||[R13_] + ([_DX] * s) + disp8||[R14_] + ([_DX] * s) + disp8||[R15_] + ([_DX] * s) + disp8
|-
! 0 !! b011
|[R8_] + ([_BX] * s) + disp8||[R9_] + ([_BX] * s) + disp8||[R10_] + ([_BX] * s) + disp8||[R11_] + ([_BX] * s) + disp8||[R12_] + ([_BX] * s) + disp8||[R13_] + ([_BX] * s) + disp8||[R14_] + ([_BX] * s) + disp8||[R15_] + ([_BX] * s) + disp8
|-
! 0 !! b100
|[R8_] + disp8||[R9_] + disp8||[R10_] + disp8||[R11_] + disp8||[R12_] + disp8||[R13_] + disp8||[R14_] + disp8||[R15_] + disp8
|-
! 0 !! b101
|[R8_] + ([_BP] * s) + disp8||[R9_] + ([_BP] * s) + disp8||[R10_] + ([_BP] * s) + disp8||[R11_] + ([_BP] * s) + disp8||[R12_] + ([_BP] * s) + disp8||[R13_] + ([_BP] * s) + disp8||[R14_] + ([_BP] * s) + disp8||[R15_] + ([_BP] * s) + disp8
|-
! 0 !! b110
|[R8_] + ([_SI] * s) + disp8||[R9_] + ([_SI] * s) + disp8||[R10_] + ([_SI] * s) + disp8||[R11_] + ([_SI] * s) + disp8||[R12_] + ([_SI] * s) + disp8||[R13_] + ([_SI] * s) + disp8||[R14_] + ([_SI] * s) + disp8||[R15_] + ([_SI] * s) + disp8
|-
! 0 !! b111
|[R8_] + ([_DI] * s) + disp8||[R9_] + ([_DI] * s) + disp8||[R10_] + ([_DI] * s) + disp8||[R11_] + ([_DI] * s) + disp8||[R12_] + ([_DI] * s) + disp8||[R13_] + ([_DI] * s) + disp8||[R14_] + ([_DI] * s) + disp8||[R15_] + ([_DI] * s) + disp8
|-
! 1 !! b000
|[R8_] + ([R8_] * s) + disp8||[R9_] + ([R8_] * s) + disp8||[R10_] + ([R8_] * s) + disp8||[R11_] + ([R8_] * s) + disp8||[R12_] + ([R8_] * s) + disp8||[R13_] + ([R8_] * s) + disp8||[R14_] + ([R8_] * s) + disp8||[R15_] + ([R8_] * s) + disp8
|-
! 1 !! b001
|[R8_] + ([R9_] * s) + disp8||[R9_] + ([R9_] * s) + disp8||[R10_] + ([R9_] * s) + disp8||[R11_] + ([R9_] * s) + disp8||[R12_] + ([R9_] * s) + disp8||[R13_] + ([R9_] * s) + disp8||[R14_] + ([R9_] * s) + disp8||[R15_] + ([R9_] * s) + disp8
|-
! 1 !! b010
|[R8_] + ([R10_] * s) + disp8||[R9_] + ([R10_] * s) + disp8||[R10_] + ([R10_] * s) + disp8||[R11_] + ([R10_] * s) + disp8||[R12_] + ([R10_] * s) + disp8||[R13_] + ([R10_] * s) + disp8||[R14_] + ([R10_] * s) + disp8||[R15_] + ([R10_] * s) + disp8
|-
! 1 !! b011
|[R8_] + ([R11_] * s) + disp8||[R9_] + ([R11_] * s) + disp8||[R10_] + ([R11_] * s) + disp8||[R11_] + ([R11_] * s) + disp8||[R12_] + ([R11_] * s) + disp8||[R13_] + ([R11_] * s) + disp8||[R14_] + ([R11_] * s) + disp8||[R15_] + ([R11_] * s) + disp8
|-
! 1 !! b100
|[R8_] + ([R12_] * s) + disp8||[R9_] + ([R12_] * s) + disp8||[R10_] + ([R12_] * s) + disp8||[R11_] + ([R12_] * s) + disp8||[R12_] + ([R12_] * s) + disp8||[R13_] + ([R12_] * s) + disp8||[R14_] + ([R12_] * s) + disp8||[R15_] + ([R12_] * s) + disp8
|-
! 1 !! b101
|[R8_] + ([R13_] * s) + disp8||[R9_] + ([R13_] * s) + disp8||[R10_] + ([R13_] * s) + disp8||[R11_] + ([R13_] * s) + disp8||[R12_] + ([R13_] * s) + disp8||[R13_] + ([R13_] * s) + disp8||[R14_] + ([R13_] * s) + disp8||[R15_] + ([R13_] * s) + disp8
|-
! 1 !! b110
|[R8_] + ([R14_] * s) + disp8||[R9_] + ([R14_] * s) + disp8||[R10_] + ([R14_] * s) + disp8||[R11_] + ([R14_] * s) + disp8||[R12_] + ([R14_] * s) + disp8||[R13_] + ([R14_] * s) + disp8||[R14_] + ([R14_] * s) + disp8||[R15_] + ([R14_] * s) + disp8
|-
! 1 !! b111
|[R8_] + ([R15_] * s) + disp8||[R9_] + ([R15_] * s) + disp8||[R10_] + ([R15_] * s) + disp8||[R11_] + ([R15_] * s) + disp8||[R12_] + ([R15_] * s) + disp8||[R13_] + ([R15_] * s) + disp8||[R14_] + ([R15_] * s) + disp8||[R15_] + ([R15_] * s) + disp8
|-
| colspan="11" style="background-color: white; border-top: solid 2px black; border-bottom: solid 2px black; border-left: none; border-right: none;" |
|-
! !! !! !! colspan="8" | REX.B = 0
|-
! Mod
! X
! Index
! Base=b000
! b001
! b010
! b011
! b100
! b101
! b110
! b111
|-
! rowspan="16" | b10 !! 0 !! b000
|[_AX] + ([_AX] * s) + disp32||[_CX] + ([_AX] * s) + disp32||[_DX] + ([_AX] * s) + disp32||[_BX] + ([_AX] * s) + disp32||[_SP] + ([_AX] * s) + disp32||[_BP] + ([_AX] * s) + disp32||[_SI] + ([_AX] * s) + disp32||[_DI] + ([_AX] * s) + disp32
|-
! 0 !! b001
|[_AX] + ([_CX] * s) + disp32||[_CX] + ([_CX] * s) + disp32||[_DX] + ([_CX] * s) + disp32||[_BX] + ([_CX] * s) + disp32||[_SP] + ([_CX] * s) + disp32||[_BP] + ([_CX] * s) + disp32||[_SI] + ([_CX] * s) + disp32||[_DI] + ([_CX] * s) + disp32
|-
! 0 !! b010
|[_AX] + ([_DX] * s) + disp32||[_CX] + ([_DX] * s) + disp32||[_DX] + ([_DX] * s) + disp32||[_BX] + ([_DX] * s) + disp32||[_SP] + ([_DX] * s) + disp32||[_BP] + ([_DX] * s) + disp32||[_SI] + ([_DX] * s) + disp32||[_DI] + ([_DX] * s) + disp32
|-
! 0 !! b011
|[_AX] + ([_BX] * s) + disp32||[_CX] + ([_BX] * s) + disp32||[_DX] + ([_BX] * s) + disp32||[_BX] + ([_BX] * s) + disp32||[_SP] + ([_BX] * s) + disp32||[_BP] + ([_BX] * s) + disp32||[_SI] + ([_BX] * s) + disp32||[_DI] + ([_BX] * s) + disp32
|-
! 0 !! b100
|[_AX] + disp32||[_CX] + disp32||[_DX] + disp32||[_BX] + disp32||[_SP] + disp32||[_BP] + disp32||[_SI] + disp32||[_DI] + disp32
|-
! 0 !! b101
|[_AX] + ([_BP] * s) + disp32||[_CX] + ([_BP] * s) + disp32||[_DX] + ([_BP] * s) + disp32||[_BX] + ([_BP] * s) + disp32||[_SP] + ([_BP] * s) + disp32||[_BP] + ([_BP] * s) + disp32||[_SI] + ([_BP] * s) + disp32||[_DI] + ([_BP] * s) + disp32
|-
! 0 !! b110
|[_AX] + ([_SI] * s) + disp32||[_CX] + ([_SI] * s) + disp32||[_DX] + ([_SI] * s) + disp32||[_BX] + ([_SI] * s) + disp32||[_SP] + ([_SI] * s) + disp32||[_BP] + ([_SI] * s) + disp32||[_SI] + ([_SI] * s) + disp32||[_DI] + ([_SI] * s) + disp32
|-
! 0 !! b111
|[_AX] + ([_DI] * s) + disp32||[_CX] + ([_DI] * s) + disp32||[_DX] + ([_DI] * s) + disp32||[_BX] + ([_DI] * s) + disp32||[_SP] + ([_DI] * s) + disp32||[_BP] + ([_DI] * s) + disp32||[_SI] + ([_DI] * s) + disp32||[_DI] + ([_DI] * s) + disp32
|-
! 1 !! b000
|[_AX] + ([R8_] * s) + disp32||[_CX] + ([R8_] * s) + disp32||[_DX] + ([R8_] * s) + disp32||[_BX] + ([R8_] * s) + disp32||[_SP] + ([R8_] * s) + disp32||[_BP] + ([R8_] * s) + disp32||[_SI] + ([R8_] * s) + disp32||[_DI] + ([R8_] * s) + disp32
|-
! 1 !! b001
|[_AX] + ([R9_] * s) + disp32||[_CX] + ([R9_] * s) + disp32||[_DX] + ([R9_] * s) + disp32||[_BX] + ([R9_] * s) + disp32||[_SP] + ([R9_] * s) + disp32||[_BP] + ([R9_] * s) + disp32||[_SI] + ([R9_] * s) + disp32||[_DI] + ([R9_] * s) + disp32
|-
! 1 !! b010
|[_AX] + ([R10_] * s) + disp32||[_CX] + ([R10_] * s) + disp32||[_DX] + ([R10_] * s) + disp32||[_BX] + ([R10_] * s) + disp32||[_SP] + ([R10_] * s) + disp32||[_BP] + ([R10_] * s) + disp32||[_SI] + ([R10_] * s) + disp32||[_DI] + ([R10_] * s) + disp32
|-
! 1 !! b011
|[_AX] + ([R11_] * s) + disp32||[_CX] + ([R11_] * s) + disp32||[_DX] + ([R11_] * s) + disp32||[_BX] + ([R11_] * s) + disp32||[_SP] + ([R11_] * s) + disp32||[_BP] + ([R11_] * s) + disp32||[_SI] + ([R11_] * s) + disp32||[_DI] + ([R11_] * s) + disp32
|-
! 1 !! b100
|[_AX] + ([R12_] * s) + disp32||[_CX] + ([R12_] * s) + disp32||[_DX] + ([R12_] * s) + disp32||[_BX] + ([R12_] * s) + disp32||[_SP] + ([R12_] * s) + disp32||[_BP] + ([R12_] * s) + disp32||[_SI] + ([R12_] * s) + disp32||[_DI] + ([R12_] * s) + disp32
|-
! 1 !! b101
|[_AX] + ([R13_] * s) + disp32||[_CX] + ([R13_] * s) + disp32||[_DX] + ([R13_] * s) + disp32||[_BX] + ([R13_] * s) + disp32||[_SP] + ([R13_] * s) + disp32||[_BP] + ([R13_] * s) + disp32||[_SI] + ([R13_] * s) + disp32||[_DI] + ([R13_] * s) + disp32
|-
! 1 !! b110
|[_AX] + ([R14_] * s) + disp32||[_CX] + ([R14_] * s) + disp32||[_DX] + ([R14_] * s) + disp32||[_BX] + ([R14_] * s) + disp32||[_SP] + ([R14_] * s) + disp32||[_BP] + ([R14_] * s) + disp32||[_SI] + ([R14_] * s) + disp32||[_DI] + ([R14_] * s) + disp32
|-
! 1 !! b111
|[_AX] + ([R15_] * s) + disp32||[_CX] + ([R15_] * s) + disp32||[_DX] + ([R15_] * s) + disp32||[_BX] + ([R15_] * s) + disp32||[_SP] + ([R15_] * s) + disp32||[_BP] + ([R15_] * s) + disp32||[_SI] + ([R15_] * s) + disp32||[_DI] + ([R15_] * s) + disp32
|-
| colspan="11" style="background-color: white; border-top: solid 2px black; border-bottom: solid 2px black; border-left: none; border-right: none;" |
|-
! !! !! !! colspan="8" | REX.B = 1
|-
! Mod
! X
! Index
! Base=b000
! b001
! b010
! b011
! b100
! b101
! b110
! b111
|-
! rowspan="16" | b10 !! 0 !! b000
|[R8_] + ([_AX] * s) + disp32||[R9_] + ([_AX] * s) + disp32||[R10_] + ([_AX] * s) + disp32||[R11_] + ([_AX] * s) + disp32||[R12_] + ([_AX] * s) + disp32||[R13_] + ([_AX] * s) + disp32||[R14_] + ([_AX] * s) + disp32||[R15_] + ([_AX] * s) + disp32
|-
! 0 !! b001
|[R8_] + ([_CX] * s) + disp32||[R9_] + ([_CX] * s) + disp32||[R10_] + ([_CX] * s) + disp32||[R11_] + ([_CX] * s) + disp32||[R12_] + ([_CX] * s) + disp32||[R13_] + ([_CX] * s) + disp32||[R14_] + ([_CX] * s) + disp32||[R15_] + ([_CX] * s) + disp32
|-
! 0 !! b010
|[R8_] + ([_DX] * s) + disp32||[R9_] + ([_DX] * s) + disp32||[R10_] + ([_DX] * s) + disp32||[R11_] + ([_DX] * s) + disp32||[R12_] + ([_DX] * s) + disp32||[R13_] + ([_DX] * s) + disp32||[R14_] + ([_DX] * s) + disp32||[R15_] + ([_DX] * s) + disp32
|-
! 0 !! b011
|[R8_] + ([_BX] * s) + disp32||[R9_] + ([_BX] * s) + disp32||[R10_] + ([_BX] * s) + disp32||[R11_] + ([_BX] * s) + disp32||[R12_] + ([_BX] * s) + disp32||[R13_] + ([_BX] * s) + disp32||[R14_] + ([_BX] * s) + disp32||[R15_] + ([_BX] * s) + disp32
|-
! 0 !! b100
|[R8_] + disp32||[R9_] + disp32||[R10_] + disp32||[R11_] + disp32||[R12_] + disp32||[R13_] + disp32||[R14_] + disp32||[R15_] + disp32
|-
! 0 !! b101
|[R8_] + ([_BP] * s) + disp32||[R9_] + ([_BP] * s) + disp32||[R10_] + ([_BP] * s) + disp32||[R11_] + ([_BP] * s) + disp32||[R12_] + ([_BP] * s) + disp32||[R13_] + ([_BP] * s) + disp32||[R14_] + ([_BP] * s) + disp32||[R15_] + ([_BP] * s) + disp32
|-
! 0 !! b110
|[R8_] + ([_SI] * s) + disp32||[R9_] + ([_SI] * s) + disp32||[R10_] + ([_SI] * s) + disp32||[R11_] + ([_SI] * s) + disp32||[R12_] + ([_SI] * s) + disp32||[R13_] + ([_SI] * s) + disp32||[R14_] + ([_SI] * s) + disp32||[R15_] + ([_SI] * s) + disp32
|-
! 0 !! b111
|[R8_] + ([_DI] * s) + disp32||[R9_] + ([_DI] * s) + disp32||[R10_] + ([_DI] * s) + disp32||[R11_] + ([_DI] * s) + disp32||[R12_] + ([_DI] * s) + disp32||[R13_] + ([_DI] * s) + disp32||[R14_] + ([_DI] * s) + disp32||[R15_] + ([_DI] * s) + disp32
|-
! 1 !! b000
|[R8_] + ([R8_] * s) + disp32||[R9_] + ([R8_] * s) + disp32||[R10_] + ([R8_] * s) + disp32||[R11_] + ([R8_] * s) + disp32||[R12_] + ([R8_] * s) + disp32||[R13_] + ([R8_] * s) + disp32||[R14_] + ([R8_] * s) + disp32||[R15_] + ([R8_] * s) + disp32
|-
! 1 !! b001
|[R8_] + ([R9_] * s) + disp32||[R9_] + ([R9_] * s) + disp32||[R10_] + ([R9_] * s) + disp32||[R11_] + ([R9_] * s) + disp32||[R12_] + ([R9_] * s) + disp32||[R13_] + ([R9_] * s) + disp32||[R14_] + ([R9_] * s) + disp32||[R15_] + ([R9_] * s) + disp32
|-
! 1 !! b010
|[R8_] + ([R10_] * s) + disp32||[R9_] + ([R10_] * s) + disp32||[R10_] + ([R10_] * s) + disp32||[R11_] + ([R10_] * s) + disp32||[R12_] + ([R10_] * s) + disp32||[R13_] + ([R10_] * s) + disp32||[R14_] + ([R10_] * s) + disp32||[R15_] + ([R10_] * s) + disp32
|-
! 1 !! b011
|[R8_] + ([R11_] * s) + disp32||[R9_] + ([R11_] * s) + disp32||[R10_] + ([R11_] * s) + disp32||[R11_] + ([R11_] * s) + disp32||[R12_] + ([R11_] * s) + disp32||[R13_] + ([R11_] * s) + disp32||[R14_] + ([R11_] * s) + disp32||[R15_] + ([R11_] * s) + disp32
|-
! 1 !! b100
|[R8_] + ([R12_] * s) + disp32||[R9_] + ([R12_] * s) + disp32||[R10_] + ([R12_] * s) + disp32||[R11_] + ([R12_] * s) + disp32||[R12_] + ([R12_] * s) + disp32||[R13_] + ([R12_] * s) + disp32||[R14_] + ([R12_] * s) + disp32||[R15_] + ([R12_] * s) + disp32
|-
! 1 !! b101
|[R8_] + ([R13_] * s) + disp32||[R9_] + ([R13_] * s) + disp32||[R10_] + ([R13_] * s) + disp32||[R11_] + ([R13_] * s) + disp32||[R12_] + ([R13_] * s) + disp32||[R13_] + ([R13_] * s) + disp32||[R14_] + ([R13_] * s) + disp32||[R15_] + ([R13_] * s) + disp32
|-
! 1 !! b110
|[R8_] + ([R14_] * s) + disp32||[R9_] + ([R14_] * s) + disp32||[R10_] + ([R14_] * s) + disp32||[R11_] + ([R14_] * s) + disp32||[R12_] + ([R14_] * s) + disp32||[R13_] + ([R14_] * s) + disp32||[R14_] + ([R14_] * s) + disp32||[R15_] + ([R14_] * s) + disp32
|-
! 1 !! b111
|[R8_] + ([R15_] * s) + disp32||[R9_] + ([R15_] * s) + disp32||[R10_] + ([R15_] * s) + disp32||[R11_] + ([R15_] * s) + disp32||[R12_] + ([R15_] * s) + disp32||[R13_] + ([R15_] * s) + disp32||[R14_] + ([R15_] * s) + disp32||[R15_] + ([R15_] * s) + disp32
|}
</div>
==== RIP/EIP-relative addressing ====
Addressing in AMD64 can be relative to the current instruction pointer value. This is indicated with the ''RIP'' (64-bit) and ''EIP'' (32-bit) instruction pointer registers, which are not otherwise exposed to the program and may not exist physically. RIP-relative addressing allows object files to be location independent.
== Displacement ==
The displacement value, if any, follows the ModR/M and SIB bytes discussed above. When the ModR/M or SIB tables state that a ''disp'' value is required, or without a ModR/M byte the use of ''moffset'' (AMD) or ''moffs'' (Intel) in the mnemonic syntax of the instruction, then the displacement bytes are required.
== Immediate ==
Some instructions require an immediate value. The instruction (and the operand-size column in the above table) determine the length of the immediate value. The ''imm8'' mnemonic (or 8-bit [[#Operand-size and address-size override prefix|operand-size]]) means a one byte immediate value, ''imm16'' (or 16-bit operand-size) means a two byte immediate value, ''imm32'' (or 32-bit operand-size) a four byte value and ''imm64'' (or 64-bit operand-size) an eight byte value. When an 8 byte immediate value is encoded, no displacement can be encoded.
== See Also ==
=== External References ===
* AMD64 Architecture Programmer's Manual [httphttps://www.amd.com/us-ensystem/assetsfiles/content_type/white_papers_and_tech_docsTechDocs/24594.pdf Volume 3: General-Purpose and System Instructions]
* [http://www.intel.com/products/processor/manuals/ Intel 64 and IA-32 Architectures Software Developer's Manuals]
[[Category:X86 CPU]]
[[Category:X86-64]]
| 