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VMX: Difference between revisions
Added section on error checking for VMX instructions, a short VMCS introduction and some notes on instruction requirements
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(Added section on error checking for VMX instructions, a short VMCS introduction and some notes on instruction requirements) |
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=== Executing VMXON ===
The main entry point for using VMX is through the VMXON instruction. The instruction requires a single operand of a m64 region called
uint32_t * region = (uint32_t *)allocate_4k_aligned(4096);
uint64_t region64 = (uint64_t)((size_t)(region) & 0xFFFFFFFF);
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This general process of taking a 32-bit memory address and turning it into a psuedo-64bit int (unsigned long long) will be used for all m64 operands later. VMCLEAR is another example instruction that requires the upper 32-bits of a memory address to be 0.
Long mode simply requires a 64-bit pointer to the region.
Note: '''The VMXON, VMCLEAR and VMPTRLD instruction must point to the physical address of their respective regions.'''
== VMX instruction error checking ==
VMX instructions have their own error reporting mechanism to indicate the success or failure of a given operation.
There are two flags used to signify the success or failure of a VM instruction. The carry flag(CF) and the zero flag(ZF).
If both of these flags are clear after a VM instruction was executed then it succeeded.
If the carry flag is set then current VMCS pointer is invalid.
If the zero flag is set, it indicates that the VMCS pointer is valid but there is some other error specified in the VM-instruction error field (encoding 4400h). Error numbers are listed in section 5.4 of the Intel SDM Volume 2B.
== VMCS ==
The VMCS only has two relevant fields that can be accessed at this time, a 4-byte VMCS revision ID located at byte offset 0 and a 4-byte abort indicator field located at byte offset 4. The rest of the VMCS is reserved for field data.
The revision field must be filled with the 32-bit revision Id stored in bits 0-31 of the IA32_VMX_BASIC MSR similar to the VMX region.
The abort field will simply contain a non-zero value if the VM abort occurs during a VMX exit, see section 23.7 in Intel's SDM 3B for error values.
A VMCS is loaded with the VMPTRLD instruction, which loads and activates a VMCS, and requires a 64-bit memory address as it's operand in the same format as VMXON/VMCLEAR.
asm volatile ("vmptrld %0; ":: "m" (vmcsRegion64));
The structure of the VMCS is covered in detail in Chapter 20 of the Intel SDM volume 3B (see link below). Field encodings for VMWRITE and VMREAD are covered in Appendix H of the same manual.
== References ==
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