VGA Hardware: Difference between revisions
added register info, added some memory layout info
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== VGA Registers ==
The VGA has a lot (over 300!) internal registers, while occupying only a short range in the I/O address space. To cope, many registers are indexed. This means that you fill one field with the number of the register to write, and then read or write another field to get/set the actual register's value.
All registers are accessed as 8 bit. The parts of a register that are not used should officially be preserved, although a lot of programs simply set them to zero. However, not all fields present in the VGA are documented here, so you will either look up a different reference, or preserve the undocumented fields.
In the documentation below, a port number and possibly an index is provided. The port is usually the base port for indexed registers, or the actual port for single registers. If the card is a [[PCI]] or later board, you can move the location of these registers. Consequence is that you will have to compute the new address for these registers manually.
=== Port 0x3C0 ===
This port is a confusing one: you write both the index and data bytes to the same port. The VGA keeps track of wether the next write is supposed to be the index or the data byte. However, the initial state is unknown. By reading from port 0x3DA it'll go to the index state. To read the contents, feed the index into port 0x3C0, then read the value from 0x3C1 (then read 0x3DA as it is not defined wether the VGA expects a data byte or index byte next).
=== Port 0x3C2 ===
This is the miscellaneous output register. It uses port 0x3C2 for writing, and 0x3CC for reading. Bit 0 of this register controls the location of several other registers: if cleared, port 0x3D4 is mapped to 0x3B4, and port 0x3DA is mapped to 0x3BA. For readability, only the first port is listed and bit 0 is assumed to be set.
=== Port 0x3C4, 0x3CE, 0x3D4 ===
These are the most used indexed registers. The index byte is written to the port given, then the data byte can be read/written from port+1. Some programs use a single word access instead of two byte accesses for writing, which does effectively the same. (take care of byte ordering when doing so)
Port 0x3D4 has some extra requirements - it requires bit 0 of the '''Miscellaneous Output Register''' to be set before it responds to this address (if cleared, these ports appears at 0x3B4). Also, registers 0-7 of 0x3D4 are write protected by the protect bit (bit 7 of index 0x11)
=== Port 0x3C8 ===
Port 0x3C8, 0x3C9 and 0x3C7 control the DAC. Each register in the DAC consists of 18 bits, 6 bits for each color component. To write a color, write the color index to port 0x3C8, then write 3 bytes to 0x3C9 in the order red, green, blue. If you want to write multiple consecutive DAC entries, you only need to write the first entry's index to 0x3C8 then write all values to 0x3C9 in the order red, green, blue, red, green, blue, and so on. The accessed DAC entry will automatically increment after every three bytes written. To read the DAC entries, write the index to be read to 0x3C7, then read the bytes from port 0x3C9 in a similar fashion (as with writing, the index will increment after every three bytes read)
== Video Memory Layout ==
The video memory consists of four 'planes' (individual units) of memory, each with a size of 64KB, giving the VGA 256k of video memory. Connected to it is the Sequencer, which interprets this memory to generate colors which are fed to the subsequent stages. The way colors are organized in this memory mainly depends on the color depth.
Specific details about how memory is accessed from the host is can be found by reading about the Graphics Controller, detailed information about video memory is rendered can be foundby reading about the Sequencer.
=== Memory Layout in 16-color graphics modes ===
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The Plane Write Enable register is used to choose the plane to be written, then the memory can be written by written by accessing the corresponding address in memory.
=== Memory Layout in 256-color graphics modes ===
In this mode, each byte of video memory describes exactly one pixel. Pixels are generated by increasing address in linear mode, with all colors taken from plane 0. In planar mode (Also known as Mode X) each address describes 4 consecutive pixels, one from each plane. Plane 0 describing the first pixel, plane 1 the next, and so on.
In linear mode, each byte in host memory corresponds to one pixel on the display, making this mode very easy to use. Mode X requires the use of Plane Write Enable register to select the plane to be written.
=== Memory Layout in text modes ===
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Although 32 bytes are reserved for each character, only 14 are commonly in used.
Planes 0 and 1 are written directly from video memory. Plane 0 is accessed on even addresses, plane 1 is accessed on odd addresses, with each consecutive word describing the next character.
=== Memory Layoud in 4-bit modes ===
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