972
edits
VGA Hardware: Difference between revisions
m
no edit summary
| [unchecked revision] | [unchecked revision] |
(added sequencer shift modes) |
mNo edit summary |
||
| (37 intermediate revisions by 19 users not shown) | |||
Line 1:
{{
Even though VGA is old, many modern graphics cards are compatible with it, including NVidia and ATI cards. This can make writing a VGA driver rather attractive. The amount of compatibility varies however, so never assume a card is compatible without proper hardware detection.
Apart from real machines, several emulators and virtual machines provide VGA emulation: [[Bochs]], [[QEMU]] and [[Microsoft Virtual PC]] to name a few. After 2011 video card manufacturers begun to drop VGA compatibility in favour of [[GOP]] under [[UEFI]] (VirtualBox UEFI and TianoCore both supports that).
== Overview ==
While the VGA chip is quite a simple piece of hardware compared to modern video equipment, it is possibly one of the more complicated devices to program for, and especially in the old days knowing your way around this particular device was sufficient for establishing quite a reputation. While currently a legacy device, it is a good place to begin practicing your video driver skills. While a full-blown VGA driver might make an USB controller look trivial, there are fortunately many shortcuts available for taking.
=== What's not covered ===
While this page tries to be a complete overview on what the VGA can do, it does not fully cover the whole set of graphics. After all, a video card only turns bytes in its memory into a signal on the connector on its backside. Determining what bytes to put in memory is only barely touched in the wiki in general — there are examples of plotting pixels and setting individual characters but your OS will determine what pixels are formed by an image and which characters are part of your title screen. On the remote end, monitors have their own way of dealing with signals. A lot of those settings dictated by monitors are needed by the video card, and each resolution comes with its own set of settings. You can find out your own set of settings by [[Video Signals And Timing|using a set of equations]], but you can skip that step and reuse one of the examples provided at the [[VGA_Hardware#Sample_Register_Settings|example settings]] instead. The [[VGA_Hardware#The_CRT_Controller|CRTC chapter]] explains them in detail.
=== Getting started ===
There's a fair share of [[VGA Resources|modesetting code available]] around the web. The basic steps involve calculating the needed register values, writing them to the VGA, then continue with drawing. You'll need:
* Port I/O: The VGA needs 8-bit read/writes, and 16-bit writes.
* MMIO: The VGA uses uncached byte accesses to 0xA0000-0xBFFFF. In several cases, larger writes are also allowed.
* Functions to [[VGA_Hardware#VGA_Registers|read and write registers]] for each VGA component - since there are many more registers than there are ports you will need a wrapper for this.
* A structure that contains the VGA display settings. For a nice list of things you want to set, you can use the example register settings part. Keep in mind that you might also want a structure for things that change during drawing, such as colours and offsets.
* A function that writes that structure to the device
* A function that fills out that structure. You can also use a hardcoded structure initially.
=== Hardware components ===
The VGA can be divided in several parts. Historically, the predecessor of the VGA - the EGA - had several chips to perform each part in the system. These chips could be configured to your liking using the I/O Bus. On the VGA, these have been merged into one chip (with the exception of the DAC).
The following diagram shows which units are responsible for which parts:
[[Image:VGA overview.gif|Overview of VGA Hardware|325px]]
This diagram is, however,
== VGA Registers ==
Line 45 ⟶ 35:
All registers are accessed as 8 bit. The parts of a register that are not used should officially be preserved, although a lot of programs simply set them to zero. However, not all fields present in the VGA are documented here, so you will either look up a different reference, or preserve the undocumented fields.
In the documentation below, a port number and possibly an index is provided. The port is usually the base port for indexed registers, or the actual port for single registers.
Note that [[PCI]] boards do *not* report the VGA addresses in their configuration space, and that the addresses can not be remapped. It is therefore not possible to properly operate two cards in VGA mode at the same time.
=== Port 0x3C0 ===
Line 54 ⟶ 46:
=== Port 0x3C4, 0x3CE, 0x3D4 ===
These are the most used indexed registers. The index byte is written to the port given, then the data byte can be read/written from port+1. Some programs use a single
Port 0x3D4 has some extra requirements - it requires bit 0 of the '''Miscellaneous Output Register''' to be set before it responds to this address (if cleared, these ports appears at 0x3B4). Also, registers 0-7 of 0x3D4 are write protected by the protect bit (bit 7 of index 0x11)
Line 144 ⟶ 136:
|}
The Plane Write Enable register is used to choose the plane to be written, then the memory can be
=== Memory Layout in 256-color graphics modes ===
In this mode, each byte of video memory describes exactly one pixel. Pixels are generated by increasing address in linear mode, with all colors taken from plane 0. In planar mode (Also known as Mode X) each address describes 4 consecutive pixels, one from each plane. Plane 0 describing the first pixel, plane 1 the next, and so on. Technically speaking this is what always happens, but the standard 320x200x256 mode "chains" the planes such that 2 lowest order bits select the plane and the memory thus appears linear.
In linear mode, each byte in host memory corresponds to one pixel on the display, making this mode very easy to use. Mode X requires the use of Plane Write Enable register to select the plane to be written.
Line 157 ⟶ 149:
Plane 2 contains the font data. For each of the 256 available characters this plane has 32 bytes reserved. Each byte represents one horizontal cross section through each character. The first byte of each group defines the top line, each next byte describes the rows below it. For every set bit, the foreground color is used, For every cleared bit, the background color is used.
Although 32 bytes are reserved for each character, only 16, 14, or 8 of them are commonly
Planes 0 and 1 are
=== Memory Layout in 4-
The CGA was limited to 4 concurrent colors, with two bits each. The EGA adds two extra bits by adding a pair of extra planes, increasing from the old two to the current four planes per pixel. If you want a 4-color mode that means you just should not touch planes 2 + 3.
'''Todo: determine the b/w/d, shift mode and odd/even mode for CGA compatibility (guesstimated at word mode, interleaved shift, odd/even enabled, i.e. equivalent to text mode except for the alphanumeric bit)'''
== The Graphics Controller ==
Line 173 ⟶ 167:
These modes seem to be consistent among all VGA compatibles and emulators I've tested:
* Mode 3 (Text mode) (right now I can only set it by keeping a state dump of VGA registers of the old mode)
* Mode 11h (Planar 16 color mode)
* Mode 13h (Linear 256 color mode)
* Mode X (Planar 256 color mode)
I have yet to write code that enters the following standard modes on all hardware
* Mode
The Graphics Controller consists of of some addressing logic, and some specific read/write logic.
Line 219 ⟶ 214:
==== Chain 4 Bit ====
The Chain-4 bit changes accesses to video mode from a planar mode when clear to a linear mode when set. While under common circumstances this bit is emulated properly, the way this bit actually works is however very different among implementations (especially emulators) and can have strange effects if you are unaware of it. What works in all cases, is if chain-4 matches the other settings that are common for established modes (i.e. if you enable chain-4, also make sure the other registers match the expected values for mode 13). Here is a list of differences between various implementations of Chain-4. Real hardware has so far proven to be consistent with the officially documented behavior.
{| {{Wikitable}}
Line 261 ⟶ 257:
plane = addr & 0x0003; // lower bits
offset = addr >> 2; // only the first 16k of each page gets written.
Note the fact that in Bochs, Chain-4 alters the physical display of the screen (equivalent to what doubleword mode normally does). This makes Bochs possibly troublesome since you only need to toggle this bit to enter Mode-X, while real hardware also requires that you change doubleword mode into byte mode.
==== Odd/Even Disable Bit ====
Line 273 ⟶ 271:
write (plane2, offset); // write to the other plane
This matches the NVidia card
offset = addr & 0xfff'''f'''; // generate the offset
Line 281 ⟶ 279:
=== Read/Write logic ===
The Read/Write Logic performs several operations on the written/read data, and a set of internal registers called the latches. Reading from video memory loads these latches with the value emitted by video memory. Write operations use the latches as an additional data source, apart from the data written from the host processor.
The read/write logic has several different operation modes. These can be chosen by setting the Graphics Mode register. The VGA has four write modes and 2 read modes, which can be set independently. By default, the VGA operates in read mode 0 and write mode 0 in such a fashion that all written data goes straight to memory, and read data from each plane is ORed together.
Registers involved:
Line 355 ⟶ 352:
'''Todo: Study effects of multibyte reads/writes on logic and latch operation'''
==== The Latches ====
Probably the most interesting part of the VGA's internal wiring is the presence of the data latches. In the old times, the VGA could only accept 8 bits at a time. The latches hold 4x8 bits, and are used as a temporary register for VGA reads and writes. By putting that register to good use, a DOS-era programmer could well exceed the data transfer rate that the 8-bit bus was capable of, and instead use the 32-bit pipeline onboard the video card.
The latches are written to whenever a load from video memory occurs. An address is supplied to video memory, which emits the 4 bytes, one for each plane, into the latches. From there, the video card determines what to send to the CPU. The latches are used again when writing to video memory. Together with the various read and write modes, the latches allowed video-to-video transfers, pattern and raster operations, as well as supplying original data for doing partial writes.
==== Write Mode 0 ====
Line 387 ⟶ 389:
* The Memory Plane Write Enable field is ANDed with the input from the address logic. For each set bit in the result, the corresponding plane is loaded with the result.
==== Write mode 3 ====
Write mode 3 can, among others, be used for transparent writes with a constant color
[[Image:VGA gc write3.gif|Write mode 3 logic]]
'''Todo: thorough testing. This is currently an unverified interpretation of existing docs'''
When a byte is written:
* The input byte is rotated right by the amount specified in Rotate Count, with all bits shifted off being fed into bit 7
* The resulting value is ANDed with the Bit Mask Register, resulting in the bit mask to be applied.
* Each plane takes one bit from the Set/Reset Value register, and turns it into either 0x00 (if set) or 0xff (if clear)
* The computed bit mask is checked, for each set bit the corresponding bit from the set/reset logic is forwarded. If the bit is clear the bit is taken directly from the Latch. The result is sent towards memory.
* Finally, The Memory Plane Write Enable field and the input line from the address logic are ANDed together. The bits that remain set are the planes that are actually written.
''' Todo: more write modes, read modes '''
== The Sequencer ==
The Sequencer is responsible to convert video memory to color indexes. Like the graphics controller, it has some special addressing logic, which is designed to iterate over the memory in a sensible manner to produce images out of video memory data.
The Sequencer either operates in text (alphanumeric) mode or graphics mode
=== Alphanumeric Mode ===
In alphanumeric mode the four planes are assigned distinct tasks. Plane 0 contains character data, while plane 1 contains Attribute data. In a standard text mode, these planes are interleaved into host memory. Plane 2 holds the font data. When displaying text data, the sequencer loads the character/attribute pair for the current set of eight pixels, after which it uses the value for byte 0 to look up the corresponding character in plane 2 and adds the character line to get the font data needed. It then pops out the bits from MSB to LSB, generating the chosen foreground color when a 1 is encountered, and the background color when a 0 is encountered.
In typical text modes, the stored font is not directly accessible and needs some [[VGA Fonts|changes in addressing logic]] to be read or written.
'''TODO: schematics'''
'''TODO: testing'''
=== Graphics Mode ===
Line 402 ⟶ 424:
The shift logic has three operating modes: single, interleaved and 256-color shift. Although the VGA 'supports' various color depths, these are basically varations on 16-color modes.
==== Shift modes ====
While going through memory, the sequencer reads in a 4 bytes at a time from each of the four planes, then outputs 8 pixel colors. The VGA has three distinct modes of grouping this data into pixel values. The setting depends on two bits in a VGA register: the 256-color shift and interleaved shift bits. when both are off, Single shift mode is selected, otherwise the corresponding mode is used (256 color shift mode takes precedence over interleaved shift mode)
{| {{Wikitable}}
|-
! Register Name
! Port
! Index
! 7
! 6
! 5
! 4
! 3
! 2
! 1
! 0
|-
| Graphics Mode Register
| 0x3CE
| 0x05
|
| 256-Color Shift
| Interleaved Shift
|
|
|
|
|
|}
* Single shift mode
:This mode is used in 16 color modes. For each pixel, one bit is popped off each plane and put together to form the value of a pixel. An example is given in [[VGA Hardware#Memory Layout in 16-color graphics modes|Memory Layout in 16-color graphics modes]]
* Interleaved Shift Mode
:This mode makes 4-color modes relatively easy: 2 bits are popped off the most significant side of plane 0. The same is done with plane 2, which become the most significant bits (in 4-color modes, these are zero) After 4 pixels being popped from planes 0 and 2, the same is done with plane 1 and 3, until all 8 pixels have been generated.
* 256-Color Shift Mode
:This mode causes 4 bits to be popped of each time. Plane 0 gives the first two pixels, Plane 1 the next two and so on. However, it is not defined in which order this happens. Because this mode is normally used solely in 256-color modes where the color logic will merge two 4-bits pixels together to form one 8-bit pixel, the communication inbetween is not certain. However, the bits can only be shifted out one of two possible sides, and supporting two possibilities can be overseen. Another problem to this method is, you can not detect which method is used without user intervention or keeping a list. Either way, this method either shifts left (from the msb) or right (from the lsb). If you know the ordering of your video card, you can create a linear 16-bit color mode.
For each group of pixels, the sequencer calculates the address in video memory where to load the data from. This address is calculated in three steps:
First the starting address of video memory is calculated: '''TODO'''
After that a scanline is rendered. The first address is read and the contents is split into pixels. Then the address is incremented by either 1, 2 or 4 for the next set of pixels until the scanline completes (the consequence of this is that each scanline is a multiple of eight pixels wide). The increment depends on wether the VGA is operating in "byte mode", "word mode", or "doubleword mode". These can be set using two bits: (doubleword modes takes precedence over byte/word mode)
'''TODO: Registers'''
Once a scanline is complete, the original value at the start of the scanline is loaded, and the scanline counter is incremented. The VGA then does one of the following:
* Add the virtual width to the offset (and going to the next sequence of pixel data in memory). You can change the virtual width to change the amount of free data between scanlines, which can be useful for scrolling screens.
* Leave the value unchanged (and draw the same scanline again, identically). This is done when doublescanning '''TODO'''
* Reset the address to 0 (and start rendering from a different location in video memory) This can be used to create splitscreens '''TODO'''
== Color Logic ==
Line 587 ⟶ 647:
==== Timing Model ====
The horizontal timing registers are based on a unit called 'character' (As they match one character in text mode). Each character equals 8 ('''9/8 Dot Mode''' is set) or 9 ('''9/8 Dot Mode''' is clear) pixels. Each scanline contains '''Horizontal Total''' + 5 characters, zero based. '''Horizontal Display End''' tells us the last character that is calculated from memory (i.e. the horizontal resolution in characters minus one). '''Horizontal Blanking Start''' and '''Horizontal Retrace Start''' give us
The vertical timing is similar, apart from the fact that these registers operate on scan lines (pixels) instead of characters. The '''Vertical Retrace End''' and '''Vertical Blank End''' registers work also similar, although they are different sizes. The Retrace End is 4 bits wide (AND with 0xF, period is 1-15 scanlines), The Blank End size is at least 7 bits (some say its 8, some say its 7), so the value is computed by ANDing with 0xFF, with the period ranging from 1-127 scanlines. As with horizontal timing, at least one scan line of overscan must be present to avoid possible artefacts.
Line 602 ⟶ 662:
==== Sample timing scheme ====
640x480 (16
* Timing: 25MHz dot clock, 8 pixels per character
* Totals: 800 pixels horizontally, (100 characters), 524 scan lines
Line 615 ⟶ 675:
Which should be VGA compatible
== Sample Register Settings ==
These are the register values that can be loaded into the VGA to set a standard mode. Note that you should unlock the CRTC and disable output before loading these registers, and afterwards restoring these to be nice for old monitors that are around.
The pseudocode for changing modes is roughly as follows:
DisableDisplay // disable output
UnlockCRTC // unlock registers
LoadRegisters // load registers
ClearScreen // clear the screen contents
LoadFonts // and for text mode, load fonts
// note that this may need to alter GC settings
// so be sure to restore those after that
LockCRTC // optional: lock the registers again
EnableDisplay // make sure there is output
=== List of register settings ===
{| {{wikitable}}
|-
! Register name
! port
! index
! mode 3h (80x25 text mode)
! mode 12h (640x480 planar 16 color mode)
! mode 13h (320x200 linear 256-color mode)
! mode X (320x240 planar 256 color mode)
|-
| Mode Control
| 0x3C0
| 0x10
| 0x0C
| 0x01
| 0x41
| 0x41
|-
| Overscan Register
| 0x3C0
| 0x11
| 0x00
| 0x00
| 0x00
| 0x00
|-
| Color Plane Enable
| 0x3C0
| 0x12
| 0x0F
| 0x0F
| 0x0F
| 0x0F
|-
| Horizontal Panning
| 0x3C0
| 0x13
| 0x08
| 0x00
| 0x00
| 0x00
|-
| Color Select
| 0x3C0
| 0x14
| 0x00
| 0x00
| 0x00
| 0x00
|-
| Miscellaneous Output Register
| 0x3C2
| N/A
| 0x67
| 0xE3
| 0x63
| 0xE3
|-
| Clock Mode Register
| 0x3C4
| 0x01
| 0x00
| 0x01
| 0x01
| 0x01
|-
| Character select
| 0x3C4
| 0x03
| 0x00
| 0x00
| 0x00
| 0x00
|-
| Memory Mode Register
| 0x3C4
| 0x04
| 0x07
| 0x02
| 0x0E
| 0x06
|-
| Mode Register
| 0x3CE
| 0x05
| 0x10
| 0x00
| 0x40
| 0x40
|-
| Miscellaneous Register
| 0x3CE
| 0x06
| 0x0E
| 0x05
| 0x05
| 0x05
|-
| Horizontal Total
| 0x3D4
| 0x00
| 0x5F
| 0x5F
| 0x5F
| 0x5F
|-
| Horizontal Display Enable End
| 0x3D4
| 0x01
| 0x4F
| 0x4F
| 0x4F
| 0x4F
|-
| Horizontal Blank Start
| 0x3D4
| 0x02
| 0x50
| 0x50
| 0x50
| 0x50
|-
| Horizontal Blank End
| 0x3D4
| 0x03
| 0x82
| 0x82
| 0x82
| 0x82
|-
| Horizontal Retrace Start
| 0x3D4
| 0x04
| 0x55
| 0x54
| 0x54
| 0x54
|-
| Horizontal Retrace End
| 0x3D4
| 0x05
| 0x81
| 0x80
| 0x80
| 0x80
|-
| Vertical Total
| 0x3D4
| 0x06
| 0xBF
| 0x0B
| 0xBF
| 0x0D
|-
| Overflow Register
| 0x3D4
| 0x07
| 0x1F
| 0x3E
| 0x1F
| 0x3E
|-
| Preset row scan
| 0x3D4
| 0x08
| 0x00
| 0x00
| 0x00
| 0x00
|-
| Maximum Scan Line
| 0x3D4
| 0x09
| 0x4F
| 0x40
| 0x41
| 0x41
|-
| Vertical Retrace Start
| 0x3D4
| 0x10
| 0x9C
| 0xEA
| 0x9C
| 0xEA
|-
| Vertical Retrace End
| 0x3D4
| 0x11
| 0x8E
| 0x8C
| 0x8E
| 0xAC
|-
| Vertical Display Enable End
| 0x3D4
| 0x12
| 0x8F
| 0xDF
| 0x8F
| 0xDF
|-
| Logical Width
| 0x3D4
| 0x13
| 0x28
| 0x28
| 0x28
| 0x28
|-
| Underline Location
| 0x3D4
| 0x14
| 0x1F
| 0x00
| 0x40
| 0x00
|-
| Vertical Blank Start
| 0x3D4
| 0x15
| 0x96
| 0xE7
| 0x96
| 0xE7
|-
| Vertical Blank End
| 0x3D4
| 0x16
| 0xB9
| 0x04
| 0xB9
| 0x06
|-
| Mode Control
| 0x3D4
| 0x17
| 0xA3
| 0xE3
| 0xA3
| 0xE3
|}
== See Also ==
=== External Links ===
* http://tinyvga.com/vga-timing — VGA Signal Timing
* http://www.osdever.net/FreeVGA/vga/vga.htm — includes some things not explained here
[[Category:VGA]]
[[Category:Video]]
[[Category:Hardware]]
| |||