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User:Greasemonkey/Intel GenX: Difference between revisions
→Gen4 "Bearlake-C" (G35?) and onwards
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===Allocating space for the GTT===
====Early Gen4
Allocate a block of memory in the stolen memory space. 512KB is the largest you can use for the GTT, and allows for a 512MB virtual addressing space. Ensure that the block of memory is aligned with its size.
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Also note that direct access to the stolen memory via GMADR also uses the physical unmapped addresses.
====Gen4 "Bearlake-C" (G35?) and onwards====
Don't allocate it. The chip allocates it for you. Just leave the upper 31:12 in PGTBL_CTL intact when you mess with it. Once you have identity paging in place, set the lower bit.
Of course, if you are paranoid, you can always allocate some memory anyway.
Paging types above are as per pre-Gen6. Gen6 has different paging types, apparently.
===Identity paging===
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