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User:Greasemonkey/Intel GenX: Difference between revisions
→Gen4 "Bearlake-C" (G35?) and onwards
(GTT is working) |
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GMAs tend to be advertised as at least two functions, so you may wish to check Function 1 as well. HDs tend to be advertised as just one.
Either way, there appears to be no difference between using BAR0 of Function 0 and BAR0 of Function 1, and only Function 0 gives
With that said, make sure you check the IDs to ensure that they match hardware that you've actually tested. Different GPUs have different bugs and thus require different workarounds - even when they're within the same family.
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Here's the information, assuming you are accessing everything through Function 0:
* uint64_t @ PCI 0x10: Location of MMIO registers. (XXX: for devices with a Function 1, this appears to do more than just MMIO registers - Function 1 should be able to provide a space with "just" MMIO registers.)
* uint64_t @ PCI 0x18: Location of
The 64-bit pointers have the lower 4 bits set to 0x4, so remember to mask it out before you use it, and remember to maintain that mask before writing back.
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</pre>
With the above config, your framebuffer should be located at the start of
===Setting monitor timings===
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It's possible to start the ring buffer and then advance the tail when you have a new command or batch of commands.
RING_BUFFER_START denotes the address relative to that
RING_BUFFER_HEAD and RING_BUFFER_TAIL need to be given byte offsets, so if you add, say, two DWords, you'd add 8 to RING_BUFFER_TAIL.
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);
genx_rb_push(((screen_height)<<16)|((screen_width)<<2)); // height in scanlines, width in bytes
genx_rb_push(
genx_rb_push(0x00330066); // XXRRGGBB - HTML colour #330066
</pre>
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genx_rb_push((0<<16) | (0)); // Y1:X1 top-left
genx_rb_push(((screen_height)<<16)|((screen_width))); // Y2:X2 bottom-right
genx_rb_push(
genx_rb_push(0x00330066); // XXRRGGBB - HTML colour #330066
</pre>
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===Finding GTTADR===
'''Gen4 only (NOT Gen4.5!)''': 32-bit address "GTTADR" at PCI B0:D2:F0:0x1C. ''(TODO: confirm)''
'''Gen4.5 and above''': 64-bit address "GTTMMADR" at PCI B0:D2:F0:0x18 , then add 2MB (0x200000). ''(TODO: confirm the "above" bit)''
tends to use GTTADR from PCI, which is the 32-bit address at PCI+0x1C.
===Allocating space for the GTT===
====Early Gen4
Allocate a block of memory in the stolen memory space. 512KB is the largest you can use for the GTT, and allows for a 512MB virtual addressing space. Ensure that the block of memory is aligned with its size.
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Also note that direct access to the stolen memory via GMADR also uses the physical unmapped addresses.
====Gen4 "Bearlake-C" (G35?) and onwards====
Don't allocate it. The chip allocates it for you. Just leave the upper 31:12 in PGTBL_CTL intact when you mess with it. Once you have identity paging in place, set the lower bit.
Of course, if you are paranoid, you can always allocate some memory anyway.
Paging types above are as per pre-Gen6. Gen6 has different paging types, apparently.
===Identity paging===
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</pre>
===Memory-to-GPU blit (and vice versa)===
This is for a 32bpp blit.
blk_(width|height) denotes the size of the blit to perform.
(src|dest)_gtt are addresses that the GPU will feed through the Global GTT or PPGTT
(src|dest)_pitch are the image pitches in DWords.
You must ensure that the GTT has the correct paging type for the given GPU for each page that this will need to use. For Gen4, use 0 for stolen memory, and 3 for system memory.
<pre>
// SRC_COPY_BLT
genx_rb_push((2<<29) | (0x43<<22)
| (3<<20) // a:rgb mask
| 0x04
);
genx_rb_push(0
| (0<<30) // reverse X direction
| (3<<24) // bit depth
| (0xCC<<16) // raster op
| (dest_pitch*4) // dest pitch in bytes
);
genx_rb_push((blk_height<<16) | (blk_width*4)); // dest dims
genx_rb_push(dest_gtt);
genx_rb_push(0
| (src_pitch*4) // src pitch in bytes
);
genx_rb_push(src_gtt); // src addr
genx_rb_punch();
</pre>
XY_SRC_COPY_BLT and whatnot should also work just fine, including with clipping and the like.
==See Also==
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