User:Foliagecanine/Paging in Long Mode: Difference between revisions
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Created page with "Paging in Long Mode is very similar to paging in protected mode. It is based off of Physical Address Extension. == Paging Structures == === Page-map Level 4 Tables a..." |
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The S bit is dependent on whether 1GiB pages are supported. For more information on 1GiB pages, see the AMD64 Architecture Programmer's Manual section 5.3.5.
PDPTs must be 4KiB aligned.
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PDs, or Page Directories, are arrays of 512 Page Directory Entries. PDs are the level below PDPTs but above PTs.
Each Page Directory Entry is 64 bits long and uses the following format:
{| {{wikitable}}
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The lowest level of tables are Page Tables. They are arrays of 512 PTEs (Page Table Entries). Page Table Entries point to 4KiB pages.
Each Page Table
{| {{wikitable}}
! Bit(s)
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=== CR3 ===
== Determining Physical Addresses ==
[[File:LongModePagingVirtualAddressExample.png|right|x320px]]
To determine a physical address from a virtual address, the following is used:
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# Any remaining bits are ORed with the physical address to determine the final virtual address
* If at any step the P bit is not set, it will produce a #PF (see [[Exceptions#Page_Fault]]).
* If at any step the R/W bit is not set and the operation is a write, it will produce a #PF.
* If at any step the U/S bit is not set and the proccessor is not in Ring 0, it will produce a #PF.
* If at any step reserved (MBZ) bits are set to 1, it will produce a #PF.
* If at any step the NX bit is set and the operation is an instruction fetch, it will produce a #PF.
== See Also ==
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