618
edits
User:Demindiro/SBI: Difference between revisions
no edit summary
(Initial page on SBI. Describes a caveat with sbi_set_timer) |
No edit summary |
||
| (4 intermediate revisions by 2 users not shown) | |||
Line 1:
{{stub|nocat=1}}
{{In Progress|nocat=1}}
Line 38:
The timer extension has a single function <code>sbi_set_timer</code> with FID 0x00. It takes a single <code>uint64_t</code> argument.
To reset the timer, pass <code>UINT64_MAX</code>. This clears the <code>STIP</code> bit and effectively disables the timer.
{{NoteBox
| QEMU as of 6.1.0-rc3 [https://gitlab.com/qemu-project/qemu/-/issues/493 does not handle <code>UINT64_MAX</code> properly]. To fix this, apply the following patch:
<pre style="text-align:left">
diff --git a/hw/intc/sifive_clint.c b/hw/intc/sifive_clint.c
index 0f41e5ea1c..e65e71e5ec 100644
--- a/hw/intc/sifive_clint.c
+++ b/hw/intc/sifive_clint.c
@@ -61,6 +61,8 @@ static void sifive_clint_write_timecmp(RISCVCPU *cpu, uint64_t value,
/* back to ns (note args switched in muldiv64) */
next = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
muldiv64(diff, NANOSECONDS_PER_SECOND, timebase_freq);
+ /* ensure next does not overflow, as timer_mod takes a signed value */
+ next = MIN(next, INT64_MAX);
timer_mod(cpu->env.timer, next);
}
</pre>
}}
== See Also ==
Line 55 ⟶ 63:
* [https://github.com/riscv/riscv-sbi-doc/blob/master/riscv-sbi.adoc RISC-V Supervisor Binary Interface Specification]
[[:Category:RISC-V]]
[[Category:User drafts]]
| |||