Universal Host Controller Interface: Difference between revisions
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== Technical Details ==
The UHCI specification defines a set of I/O mapped registers that allow communication between the controller and the operating system. The base address for these registers can be found by searching the PCI controller for a specific VendorID/DeviceID combination, or for a specific ClassID/SubclassID/Interface combination. All UHCI [[PCI]] controllers will have a Class ID of 0x0C, a Subclass ID of 0x03, and an Interface value of 0x00. The PCI Configuration space for this device will contain the I/O port address information in BAR4. This may be different from other standards such as [[OHCI]] or [[EHCI]].
== I/O Registers ==
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! Name
! Description
! Lenght
|-
| 00 || USBCMD || Usb Command || 2 bytes
|-
| 02 || USBSTS || Usb Status || 2 bytes
|-
| 04 || USBINTR || Usb Interrupt Enable || 2 bytes
|-
| 06 || FRNUM || Frame Number || 2 bytes
|-
| 08 || FRBASEADD || Frame List Base Address || 4 bytes
|-
| 0C || SOFMOD|| Start Of Frame Modify || 1 byte
|-
| 10 || PORTSC1 || Port 1 Status/Control || 2 bytes
|-
| 12 || PORTSC2 || Port 2 Status/Control || 2 bytes
|-
|}
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| 15-8 || Reserved ||
|-
| 7 || Max Packet || 0 = Max packet size 32 bits 1 = Max packet size 64 bits
|-
| 6 || Configure||
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| 1 || Host Controller Reset ||
|-
| 0 || Run || 1 = Controller execute frame list entries
|-
|}
=== Status Register ===
You can clear this bits by writing 1 to it.
{| {{wikitable}}
! Bits
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| 15-6 || Reserved ||
|-
| 5 || Halted || 1 = bit 0 in CMD is zero 0 = bit 0 in CMD is 1
|-
| 4 || Process Error ||
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| 15-4 || Reserved ||
|-
| 3 || Short Packet || 1=Enable interrupt 0=Disable interrupt
|-
| 2 || Complete || 1=Enable interrupt 0=Disable interrupt
|-
| 1 || Resume || 1=Enable interrupt 0=Disable interrupt
|-
| 0 || Timeout CRC || 1=Enable interrupt 0=Disable interrupt
|-
|}
=== Frame Number ===
Number of processed entry of Frame List.
=== Frame List Base Address ===
32-bit physical adress of Frame List. Remember that first 12 bytes are always 0. The Frame List must contain 1024 entries.
=== Start Of Frame ===
This port set timing of frame. Should be 0x40.
=== Port 1/2 Status/Control Registers ===
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| 11-10 || Reserved ||
|-
| 9 || Reset || 1 = Device is in reset
|-
| 8 || Low Speed || 1 = Device is Low Speed
|-
| 7 || Reserved || (Must be 1)
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| 5-4 || Line Status ||
|-
| 3 || Port Enable Changed || Bit 2 value was changed, write-clear bit
|-
| 2 || Port Enabled || 1 = Device is enabled
|-
| 1 || Connected Changed || Bit 0 value was changed, write-clear bit
|-
| 0 || Connected || 1 = Some device is connected
|-
|}
== Memory structures ==
=== Frame List Entry ===
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| 31-4 || First Descriptor Address ||
|-
| 3-2 || Reserved ||
|-
| 1 || 0 = Address points to TD 1 = Address points to QH ||
|-
| 0 || 0 = Frame Is Valid 1 = Empty Frame ||
|-
|}
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! Name
! Description
! Lenght
|-
| 00 || Next Descriptor || Same as Frame Entry Above || 4 byte lenght
|-
| 04 || Status || See below || 4 byte lenght
|-
| 08 || Packet Header || See below || 4 byte lenght
|-
| 12 || Buffer Address || 32-bit address of data buffer || 4 byte lenght
|-
| 16 || System Use ||
|-
|}
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| 31-30 || Reserved ||
|-
| 29 || Short Packet Detect || 1 = If SPD, continue execution from horizontal QH pointer
|-
| 28-27 || Error Counter ||
|-
| 26 || Low Speed || 1 = This is transfer to Low speed device
|-
| 25 || Is Isochronous ||
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| 16-11 || Reserved ||
|-
| 10-0 || Actual Length || Length of transferred bytes-1
|-
|}
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! Description
|-
| 31-21 || Maximum Length || (Length - 1) so 7 for low speed, 63 for full speed
|-
| 20 || Reserved ||
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| 14-8 || Device ||
|-
| 7-0|| Packet Type || 0x69 = IN, 0xE1 = OUT, 0x2D = SETUP, other values are invalid
|-
|}
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== See Also ==
===External Links===
* [
[[Category:USB]]
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