TLB: Difference between revisions

The '''Translation Lookaside Buffer''' ('''TLB''') is a cache of memory page translations employed in many systems with memory paging capability. When the processor needs to translate a given virtual address into a physical address, the TLB is consulted first. On x86 systems, TLB misses are handled transparently by hardware. Only if the page directory/table entry is not present in-core will the operating system be notified (by the means of a page fault exception.)

 

Like a regular CPU cache, the TLB is ''mostly'' transparent. There are two cases which the operating system must be aware of.

 

The TLB is not transparently informed of changes made to paging structures. Therefore the TLB has to be flushed upon such a change. On x86 systems, this can be done by writing to the page directory base register (CR3):

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Note that changing/reloading CR3 should only need to be done when switching between process address spaces. Using it to completely flush TLBs is really quite overkill in most situations.

 

The above is more complicated in the multi-processor case. If another processor could also be affected by a page table write (because of shared memory, or multiple threads from the same process), you must also flush the TLBs on those processors. This will require some form of inter-processor communication.

 

* [http://en.wikipedia.org/wiki/Translation_lookaside_buffer The Wikipedia TLB article]