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== Usage implications ==
Like a regular CPU cache, the TLB is ''mostly'' transparent.
▲A TLB is a cache of memory translations (i.e. page table entries). When the processor needs to translate a given virtual address into a physical address, the TLB is checked first. On x86 systems, TLB misses are handled transparently by hardware. Only if the page table entry (or any higher level directory entry) is not present will the operating system be notified.
=== Modification of paging structures ===
▲Like a cache, the TLB is ''mostly'' transparent. There are some cases which the OS must be aware of:
<syntaxhighlight lang="asm">
movl %cr3,%eax
▲#:The TLB is not aware of changes you make to the page tables (at any level). If you make a change, you must flush the TLBs. On x86, this can be done by writing to the page table base register (CR3). That is:<br>
movl %eax,%cr3
</syntaxhighlight>
#:An alternate (and better) method is to use the invlpg instruction, which should be used instead of the above method when doing small mapping modifications (creation, removing, changing). Mostly, invlpg is used in functions such as "unmap" and "remap" in order to avoid the old cached lookup being used. If invlpg or some other TLB flush method had not been used, the mapping would remain cached causing potentially strange behaviour across the system.▼
#:Note that changing/reloading CR3 should only need to be done when switching between process address spaces. Using it to completely flush TLBs is really quite overkill in most situations.▼
# Multi-processor consistency▼
#:The above is more complicated in the multi-processor case. If another processor could also be affected by a page table write (because of shared memory, or multiple threads from the same process), you must also flush the TLBs on those processors. This will require some form of inter-processor communication.▼
▲
==Links==▼
* TLB at [http://en.wikipedia.org/wiki/Translation_lookaside_buffer Wikipedia]▼
However, please note that the <code>invlpg</code> instruction was introduced in the i486 ISA and is not part of the i386 ISA, thereby requiring a properly written i386-compatible kernel to use conditional inclusion of relevant code at compilation time depending on the target machine. An example routine declaration and source code follow:
<syntaxhighlight lang="c">
void vm_page_inval(void *);
</syntaxhighlight>
<syntaxhighlight lang="asm">
#include <kconfig.h>
.globl vm_page_inval
vm_page_inval:
#if TARGET_MACHINE >= TARGET_MACHINE_I486
movl 4(%esp),%eax
invlpg (%eax)
#else /* TARGET_MACHINE < TARGET_MACHINE_I486 */
movl %cr3,%eax
movl %eax,%cr3
#endif
ret
</syntaxhighlight>
▲
▲
== See Also ==
▲=== External Links ===
[[Category:X86]]
[[Category:Paging]]
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