System Management Mode: Difference between revisions
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SMM is triggered through a System Management Interrupt (SMI), a signal sent from the [[chipset]] to the CPU. During platform initialization, the firmware configures the chipset to cause a System Management Interrupt for various events that the firmware developer would like the firmware to be made aware of. The firmware also designates the region of RAM that should be used as SMRAM and specifies where the CPU should jump when an SMI occurs. During operation, the chipset detects the configured events and signals an SMI, triggering the CPU to enter SMM by jumping to the SMM entry point. The OS has no way of knowing when the chipset might signal an SMI and cannot "catch" System Management Interrupts like other interrupts. SMIs are not routed through the [[IVT]]/[[IDT]].
An OS ''can'' ask the chipset to signal an SMI, although the handling of the SMI will still be transparent. This is performed by writing to a particular [[Port IO|port]] (determined via [[ACPI]]). If the OS asks the chipset to signal an SMI and there is no reason for an SMI to be triggered at that particular moment, the firmware will not have much to do and the OS will regain control almost immediately.
== SMM and ACPI ==
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