Setting Up Paging With PAE: Difference between revisions

===Setting Up The Data Structures===

As mentioned above the 'Page-Directory-Pointer-Table' is added, which contains 4 Page-Directory-Entries

uint64_t page_dir_ptr_tab[4] __attribute__((aligned(0x20))); // must be aligned to (at least)0x20, ...

// ... turning out that you can put more of them into one page, saving memory

Keep in mind that the size of the CR3 register remains at 4byte, meaning that a PDPT must be located below 4GiB in physical memory.

 

Now we need our Page-Directory. For the sake of easiness, we'll use PSE. (2 MIB pages mapped in page directory)

// 512 entries

uint64_t page_dir[512] __attribute__((aligned(0x1000))); // must be aligned to page boundary

 

===Making it run===

Ok, now we have our structures. Let's map the first 2 MIB.

page_dir_ptr_tab[0] = (uint64_t)&page_dir | 1; // set the page directory into the PDPT and mark it present

page_dir[0] = 0b10000011; //Address=0, 2MIB, RW and present

 

Pages are mapped. Now we have to set the PAE-bit in CR4 and load the PDPT into CR3

asm volatile ("movl %%cr4, %%eax; bts $5, %%eax; movl %%eax, %%cr4" ::: "eax"); // set bit5 in CR4 to enable PAE

asm volatile ("movl %0, %%cr3" :: "r" (&page_dir_ptr_tab)); // load PDPT into CR3

 

Finally, we'll enable paging.

Simply done:

asm volatile ("movl %%cr0, %%eax; orl $0x80000000, %%eax; movl %%eax, %%cr0;" ::: "eax");

 

PAE paging should now be enabled.

 

[[Category:X86 CPU]]

[[Category:Tutorials]]