Serial Ports: Difference between revisions
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Content deleted Content added
Added First In / First Out Control Register and Interrupt Identification Register Sections (plus minor consistency edit) |
m Fix mistake in Interrupt State section and flip table for bits 2-1 and 7-6 |
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! Bit
! Bit
! Interrupt
! Priority
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====FIFO Buffer State====
{| {{wikitable}}
! Bit
! Bit
! State
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