Serial Ports: Difference between revisions
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m Fix mistake in Interrupt State section and flip table for bits 2-1 and 7-6 |
m Consistency |
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To set the port parity, set bits 3, 4 and 5 of the Line Control Register [PORT + 3].
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! Bit 5
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To communicate with a serial port in interrupt mode, the interrupt-enable-register (see table above) must be set correctly. To determine which interrupts should be enabled, a value with the following bits (0 = disabled, 1 = enabled) must be written to the interrupt-enable-register:
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! Bit 7-4
! Bit 3
! Bit 2
! Bit 1
! Bit 0
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| Reserved
| 0 || Data available▼
▲| 2 || Break/error
▲| 3 || Status change
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===First In First Out Control Register===
The First In / First Out Control Register (FCR) is for controlling the FIFO buffers. Access this register by writing to port offset +3.
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====Interrupt Trigger Level====
The Interrupt Trigger Level is used to configure how much data must be received in the FIFO Receive buffer before triggering a Received Data Available Interrupt.
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! Bit 7
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===Interrupt Identification Register===
The Interrupt Identification Register (IIR) is for identifying pending interrupts. Access this register by reading from port offset +3.
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====Interrupt State====
After Interrupt Pending is set, the Interrupt State shows the interrupt that has occurred. They have varying levels of priority, with high-value interrupts handled first, and low-value interrupts being handled last.
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! Bit 2
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