Serial Ports: Difference between revisions
m
Bot: Replace main article with main template
| [unchecked revision] | [unchecked revision] |
No edit summary |
m (Bot: Replace main article with main template) |
||
| (11 intermediate revisions by 4 users not shown) | |||
Line 39:
The addresses for COM ports can vary depending on how they are connected to the machine and how the BIOS is configured. Some BIOS configuration utilities allow you to see and set what these are, so if you in doubt for a test machine, this might be a good place to look to get you started.
For the most part, the first two COM ports will be at the addresses specified, the addresses for further COM ports
{| {{wikitable}}
! COM Port
Line 68:
! IO Port Offset
! Setting of DLAB
! I/O Access
! Register mapped to this port
|-
| +0 || 0 ||
|-
| +
|-
| +1 || 0 || Read/Write || Interrupt Enable Register.
|-
| +
|-
| +1 || 1 || Read/Write || With DLAB set to 1, this is the most significant byte of the divisor value.
|-
| +2 || - || Read || Interrupt Identification
|-
| +
|-
| +
|-
| +
|-
| +
|-
| +6 || - || Read || Modem Status Register.
|-
| +7 || - || Read/Write || Scratch Register.
|}
Line 108 ⟶ 113:
# Send the most significant byte of the divisor value to [PORT + 1].
# Clear the most significant bit of the Line Control Register.
====Line Control Register====
The Line Control register sets the general connection parameters.
{| class="wikitable"
|-
! Bit 7
! Bit 6
! Bits 5-3
! Bit 2
! Bits 1-0
|-
| Divisor Latch Access Bit
| Break Enable Bit
| Parity Bits
| Stop Bits
| Data Bits
|}
====Data Bits====
Line 127 ⟶ 150:
|}
====Stop
The serial controller can be configured to send a number of bits after each character of data. These reliable bits can be used to by the controller to verify that the sending and receiving devices are in phase.
Line 143 ⟶ 166:
|}
====Parity Bits====
The controller can be made to add or expect a parity bit at the end of each character of data transmitted. With this parity bit, if a single bit of data is inverted by interference, a parity error can be raised. The parity type can be NONE, EVEN, ODD, MARK or SPACE.
Line 153 ⟶ 176:
To set the port parity, set bits 3, 4 and 5 of the Line Control Register [PORT + 3].
{| {{wikitable}}
! Bit 5
Line 174 ⟶ 196:
To communicate with a serial port in interrupt mode, the interrupt-enable-register (see table above) must be set correctly. To determine which interrupts should be enabled, a value with the following bits (0 = disabled, 1 = enabled) must be written to the interrupt-enable-register:
{| {{wikitable}}
! Bit 7-4
! Bit 3
! Bit 2
! Bit 1
! Bit 0
|-
| Reserved
| Modem Status
| Receiver Line Status
| Transmitter Holding Register Empty
| Received Data Available
|}
===First In First Out Control Register===
The First In / First Out Control Register (FCR) is for controlling the FIFO buffers. Access this register by writing to port offset +2.
{| class="wikitable"
|-
! Bits 7-6
! Bits 5-4
! Bit 3
! Bit 2
! Bit 1
! Bit 0
|-
| Interrupt Trigger Level
| Reserved
| DMA Mode Select
| Clear Transmit FIFO
| Clear Receive FIFO
| Enable FIFO's
|}
====Clear Transmit FIFO and Clear Receive FIFO====
Bit 2 being set clears the Transmit FIFO buffer while Bit 1 being set clears the Receive FIFO buffer. Both bits will set themselves back to 0 after they are done being cleared.
====Interrupt Trigger Level====
The Interrupt Trigger Level is used to configure how much data must be received in the FIFO Receive buffer before triggering a Received Data Available Interrupt.
{| {{wikitable}}
! Bit 7
! Bit 6
! Trigger Level
|-
| 0 || 0 || 1 Byte
|-
| 0 || 1 || 4 Bytes
|-
| 1 || 0 || 8 Bytes
|-
| 1 || 1 || 14 Bytes
|}
===Interrupt Identification Register===
The Interrupt Identification Register (IIR) is for identifying pending interrupts. Access this register by reading from port offset +2.
{| class="wikitable"
|-
! Bits 7-6
! Bits 5-4
! Bit 3
! Bit 2-1
! Bit 0
|-
| FIFO Buffer State
| Reserved
| Timeout Interrupt Pending (UART 16550) or Reserved
| Interrupt State
| Interrupt Pending
|}
====Interrupt State====
After Interrupt Pending is set, the Interrupt State shows the interrupt that has occurred. They have varying levels of priority, with high-value interrupts handled first, and low-value interrupts being handled last.
{| {{wikitable}}
! Bit 2
! Bit 1
! Interrupt
! Priority
|-
| 0 || 0 || Modem Status || 4 (Lowest)
|-
| 0 || 1 || Transmitter
|-
| 1 || 0 || Received Data Available || 2
|-
| 1 || 1 || Receiver Line Status || 1 (Highest)
|}
====FIFO Buffer State====
{| {{wikitable}}
! Bit 7
! Bit 6
! State
|-
|
|-
| 0 || 1 || FIFO Enabled but Unusable
|-
|
|}
Line 228 ⟶ 334:
by the Interrupt Enable Register.
===Line
The line status register is useful to check for errors and enable polling.
{| {{wikitable}}
Line 282 ⟶ 388:
===Terminals===
Once you can send and receive bytes with confidence, you probably want to connect the serial port to a terminal (or more likely a terminal emulator these days). Those send specific byte sequences when a key is pressed, and can interpret codes to move the cursor on the screen and change color for example.
Line 289 ⟶ 395:
==Example Code==
===Initialization===
<
#define PORT 0x3f8 // COM1
Line 313 ⟶ 419:
return 0;
}
</syntaxhighlight>
Notice that the initialization code above writes to [PORT + 1] twice with different values. This is once to write to the Divisor register along with [PORT + 0] and once to write to the Interrupt register as detailed in the previous section. The second write to the Line Control register [PORT + 3] clears the DLAB again as well as setting various other bits.
===Receiving data===
<
int serial_received() {
return inb(PORT + 5) & 1;
Line 328 ⟶ 434:
return inb(PORT);
}
</syntaxhighlight>
===Sending data===
<
int is_transmit_empty() {
return inb(PORT + 5) & 0x20;
Line 342 ⟶ 448:
outb(PORT,a);
}
</syntaxhighlight>
==Glossary==
| |||