SYSENTER: Difference between revisions
| [unchecked revision] | [unchecked revision] |
Content deleted Content added
Added compatability and security information |
mNo edit summary |
||
Line 60:
For both AMD and Intel, it is up to the kernel to switch stack back to the userspace stack before executing SYSRET. This opens a race condition where the NMIs and MCEs exception handlers will be executed on a guest controlled stack. For 64bit mode, the kernel must use Interrupt Stack Tables to safely move NMIs/MCEs onto a properly designated kernel stack. For 32bit mode AMD systems, the kernel must use Task Gates for NMIs and MCEs to switch stack.
All Intel CPUs to date (2013) have a silicon bug when executing the SYSRET instruction. If a non-canonical address is present in RCX when executing SYSRET, a General Protection Fault will be taken in CPL0 with CPL3 registers. See [http://lists.xen.org/archives/html/xen-announce/2012-06/msg00001.html| Xen Security Advisory 7] for more details.
[[Category:X86 CPU]]
| |||