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RTL8139: Difference between revisions
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NB If you find your driver suddenly freezes and stops receiving interrupts and you're using kvm/qemu. Try the option -no-kvm-irqchip
The PCI vendor ID is 0x10EC and the device ID is 0x8139.
== Overview ==
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this should essentially *power on* the device.
<
outportb( ioaddr + 0x52, 0x0);
</syntaxhighlight>
==== Software Reset! ====
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initialization procedure.
<
outportb( ioaddr + 0x37, 0x10);
while( (inb(ioaddr + 0x37) & 0x10) != 0) { }
</syntaxhighlight>
==== Init Receive buffer ====
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that variables memory location to the RBSTART register (0x30).
<
//ioaddr is obtained from PCI configuration
outportd(ioaddr + 0x30, (
</syntaxhighlight>
▲ outportd(ioaddr + 0x30, (unsigned long)rx_buffer); // send dword memory location to RBSTART (0x30)
Note that 'rx_buffer' needs to be a pointer to a '''physical address'''. In this case a size of 8192 + 16 (8K + 16 bytes) is recommended, see below.
=== Set IMR + ISR ===
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a TOK or ROK IRQ happens, it actually will go through and fire up an IRQ.
<
outportw(ioaddr + 0x3C, 0x0005); // Sets the TOK and ROK bits high
</syntaxhighlight>
=== Configuring receive buffer (RCR) ===
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You can also tell the size of your RX buffer here, however if you use a 8k + 16 buffer as described before, writing zeroes is enough. To use the WRAP=1 bit, an 8K buffer must in fact be 8k+16+1500 bytes.
<
outportl(ioaddr + 0x44, 0xf | (1 << 7)); // (1 << 7) is the WRAP bit, 0xf is AB+AM+APM+AAP
</syntaxhighlight>
=== Enable Receive and Transmitter ===
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Once this is completed, then the card will start allowing packets in and/or out.
<
outportb(ioaddr + 0x37, 0x0C); // Sets the RE and TE bits high
</syntaxhighlight>
=== Transmitting Packets ===
The RTL8139 NIC uses a round robin style for transmitting packets. It has four transmit buffer (a.k.a. transmit start) registers, and four transmit status/command registers. The transmit start registers are each 32 bits long, and are in I/O offsets 0x20, 0x24, 0x28 and 0x2C. The transmit status/command registers are also each 32 bits long and are in I/O offsets 0x10, 0x14, 0x18 and 0x1C. Each pair of transmit start and status registers work together (i.e. registers 0x20 and 0x10 work together, 0x24 and 0x14 work together, etc.)
After performing a controller reset as mentioned above, the controller ignores all transmit registers except pair zero (i.e. register 0x20 for the transmit start and register 0x10 for the status/command.) After software transmits a packet using those registers, the round robin counter increments, to use pair one (i.e. register 0x24 for the transmit start and register 0x14 for the status/command.) This continues until pair number three, which is the last transmit register pair, and the counter then overflows and goes back to pair number zero. When the controller is using a specific transmit register pair, all other transmit registers are ignored, and cannot be used to transmit packets at all. Software is responsible for keeping track which pair is being used.
Each transmit start register contains the 32-bit physical address of the packet which is to be sent over the network.
Each transmit status/command register contains various bit fields that control the transmission of the packet. The table below only gives a brief about these bits. For the full format, take a look at the RTL8139 specification under "External links" below.
{| width="70%" border="1"
|-
|'''Bit Range'''
|'''Description'''
|-
|0-12
|'''Data size.''' This field contains the total size of the data to be sent across the network. The maximum value for this field is 1792, and larger numbers will cause an error.
|-
|13
|'''Own bit.''' When this bit is set to 1, the controller is idle and not performing any DMA transfers on this descriptor. The driver sets this bit to zero to tell the controller to start transmitting the packet. The bit then remains zero until the entire packet has been copied from RAM into the controller's internal memory via DMA. The default value after a reset is one. Setting this bit to zero also clears all other status bits in this register.
|-
|15
|'''Transmit OK.''' After the own bit has been set by the hardware, indicating the DMA transfer has completed, the hardware will start to transmit the packet across the actual network. This bit will be set to one after the network transmission has completed.
|}
== ISR Handler ==
When you handle an interrupt, you ''have'' to write the bit corresponding to the interrupt to reset it. The
'''Note that it is important you write to this register ''before you read any packets from your buffers'', or the write to the register will have no effect, and any other packets than the first will not be delivered to your ISR.'''
For example, this is tested and works on QEmu:
<
void rtl8139_handler(uint8_t isr, uint64_t error, uint64_t irq) {
uint16_t status = inw(io_base + 0x3e);
outw(io_base + 0x3E, 0x05);
if(status & TOK) {
// Sent
}
if (status & ROK) {
// Received
receive_packet();
}
}
</syntaxhighlight>
== Related Articles ==
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== External Links ==
* [https://github.com/omarrx024/xos/tree/master/rtl8139 xOS RTL8139 Driver] (MIT license)
* http://www.magnesium.net/~wpaul/rt/spec-8139cp(150).pdf, Datasheet for the RTL8139C
* http://www.cs.usfca.edu/~cruse/cs326f04/RTL8139D_DataSheet.pdf, Datasheet for the RTL8139D, has more information
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