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m (64-Bit Paging: fix physical => virtual for 5-level page tables) |
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When PS=0, the page table address field represents the physical address of the page table that manages the four megabytes at that point. Please note that it is very important that this address be 4-KiB aligned. This is needed, due to the fact that the last 12 bits of the 32-bit value are overwritten by access bits and such. Similarly, when PS=1, the address must be 4-MiB aligned.
* PAT, or ''''P'''age '''A'''ttribute '''T'''able'. If [https://en.wikipedia.org/wiki/Page_attribute_table PAT] is supported, then PAT along with PCD and PWT shall indicate the memory caching type. Otherwise, it is reserved and must be set to 0.
* G, or ''''G'''lobal' tells the processor not to invalidate the TLB entry corresponding to the page upon a MOV to CR3 instruction. Bit 7 (PGE) in CR4 must be set to enable global pages.
* PS, or ''''P'''age '''S'''ize' stores the page size for that specific entry. If the bit is set, then the PDE maps to a page that is 4 MiB in size. Otherwise, it maps to a 4 KiB page table. Please note that 4-MiB pages require PSE to be enabled.
* D, or ''''D'''irty' is used to determine whether a page has been written to.
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