Anonymous user
Paging: Difference between revisions
m
64-Bit Paging: fix physical => virtual for 5-level page tables
| [unchecked revision] | [unchecked revision] |
m (64-Bit Paging: fix physical => virtual for 5-level page tables) |
|||
Line 70:
[[Image:64-bit page tables1.png|thumb|Page map table entry structure (non-page-sized)]]
Paging in [[x86-64|long mode]] is similar to that of 32-bit paging, except [[PAE|Physical Address Extension]] (PAE) is required. Registers CR2 and CR3 are extended to 64 bits. Instead of just having to utilize 3 levels of page maps: page directory pointer table, page directory, and page table, a fourth page-map table is used: the level-4 page map table (PML4). This allows a processor to map 48-bit virtual addresses to 52-bit physical addresses. If level-5 page maps are supported and enabled, then a fifth page-map table, the level-5 page map table (PML5), allows the processor to map 57-bit
Virtual addresses in 64-bit mode must be '''canonical''', that is, the upper bits of the address must either be all 0s or all 1s. For systems supporting 48-bit virtual address spaces, the upper 16 bits must be the same, and for systems supporting 57-bit virtual addresses, the upper 7 bits must match. Although 32-bit code running in [[x86-64|long mode]] (compatibility mode) is still limited to 32-bit virtual addresses, they can still map to a 52-bit physical addresses.
| |||