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→32-bit Paging (Protected Mode)
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== 32-bit Paging (Protected Mode) ==
=== MMU ===
Paging is achieved through the use of the [[Memory Management Unit]] (MMU). On the x86, the MMU maps memory through a series of [[Page Tables|tables]], two to be exact. They are the paging directory (PD), and the paging table (PT).
Both [[Page Tables| tables]] contain 1024 4-byte entries, making them 4 KiB each. In the page directory, each entry points to a page table. In the page table, each entry points to a 4 KiB physical
Translation of a virtual address into a physical address first involves dividing the virtual address into three parts: the most significant 10 bits (bits 22-31) specify the index of the page directory entry, the next 10 bits (bits 12-21) specify the index of the page table entry, and the least significant 12 bits (bits 0-11) specify the page offset. The then MMU walks through the paging structures, starting with the page directory, and uses the page directory entry to locate the page table. The page table entry is used to locate the base address of the physical page frame, and the page offset is added to the physical base address to produce the physical address. If translation fails for some reason (entry is marked as not present, for example), then the processor issues a page fault.
=== Page Directory ===
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