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Setting the PS bit makes the page directory entry point directly to a 4-MiB page. There is no paging table involved in the address translation.
Note: With 4-MiB pages, whether or not bits 2120 through 13 are reserved depends on PSE being enabled and how many PSE bits are supported by the processor (PSE, PSE-36, PSE-40). [[CPUID]] should be used to determine this. Thus, the physical address must also be 4-MiB-aligned. Physical addresses above 4 GiB can only be mapped using 4 MiB PDEs.
 
=== Page Table ===
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