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→Page Map Table Entries: Added link for EFER register
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New bits have been added to page map table entries for long-mode paging:
* XD, or ''''E'''xecute '''D'''isable'. If the NXE bit (bit 11) is set in the [[CPU_Registers_x86-64#IA32_EFER|EFER register]], then instructions are not allowed to be executed at addresses within the page whenever XD is set. If EFER.NXE bit is 0, then the XD bit is reserved and should be set to 0.
* PK, or ''''P'''rotection '''K'''ey'. The protection key is a 4-bit corresponding to each virtual address that is used to control user-mode and supervisor-mode memory accesses. If the PKE bit (bit 22) in CR4 is set, then the PKRU register is used for determining access rights for user-mode based on the protection key. If the PKS bit (bit 24) is set in CR4, then the PKRS register is used for determining access rights for supervisor-mode based on the protection key. A protection key allows the system to enable/disable access rights for multiple page entries across different address spaces at once.
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