Paging: Difference between revisions

All Intel processors since Pentium Pro (with exception of the Pentium M at 400 Mhz) and all AMD since the Athlon series implement the [[PAE|Physical Address Extension]] (PAE). This feature allows you to access up to 4 PiB (2^⁵²) of RAM. You can check for this feature using [[CPUID|CPUID]]. Once checked, you can activate this feature by setting bit 5 in CR4.

For legacy 32-bit PAE, the CR3 register points to a table of 4 64-bit entries, each one pointing to a page directory made of 4096 bytes (like in normal paging), divided into 512 64-bit entries, each pointing to a 4096 byte page table, divided into 512 64bit page entries. Keep in mind that virtual address are still limited to 4 GiB (2³² bytes).

For 4-level and 5-level PAE, as used in compatibility mode and [[x86-64|long mode]], the CR3 register points to the top-level page map table: the PML4 table and PML5 table, respectively. Each of the page map tables: PML5 table, PML4 table, page directory pointer table, page directory, page table, contain 512 64-bit entries.