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Paging: Difference between revisions
→Physical Address Extension: Added description for 4-level and 5-level paging
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== Physical Address Extension ==
All Intel processors since Pentium Pro (with exception of the Pentium M at 400 Mhz) and all AMD since the Athlon series implement the [[PAE|Physical Address Extension]] (PAE). This feature allows you to access up to
For legacy 32-bit PAE, the CR3 register points to a table of 4 64-bit entries, each one pointing to a page directory made of 4096 bytes (like in normal paging), divided into 512 64-bit entries, each pointing to a 4096 byte page table, divided into 512 64bit page entries.
If paging is to be used, then PAE must be enabled before entering long mode. Failure to do so will trigger a general protection fault.▼
For 4-level and 5-level PAE, as used in compatibility mode and long mode, the CR3 register points to the top-level page map table: the PML4 table and PML5 table, respectively. Each of the page map tables: PML5 table, PML4 table, page directory pointer table, page directory, page table, contain 512 64-bit entries.
▲If paging is
== Usage ==
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