Paging: Difference between revisions

[[Image:Page dirPage_directory_entry.png|frame|A Page Directory Entry]]

TheWhen PS=0, the page table address field represents the physical address of the page table that manages the four megabytes at that point. Please note that it is very important that this address be 4-KiB aligned. This is needed, due to the fact that the last 12 bits of the 32-bit value are overwritten by access bits and such. Similarly, when PS=1, the address must be 4-MiB aligned.

* SG, or 'Page '''S'G''ize'lobal storestells the pageprocessor sizenot forto thatinvalidate specificthe TLB entry. Ifcorresponding to the bitpage isupon set,a thenMOV pagesto areCR3 4instruction. MiBBit in7 size.(PGE) Otherwise,in theyCR4 aremust 4be KiB.set Pleaseto noteenable that 4-MiBglobal pages require PSE to be enabled.

* DPCD, is the 'Cache '''D'''isableDisable' bit. If the bit is set, the page will not be cached. Otherwise, it will be.

* WPWT, the controls ''''W'''riteWrite-Through' abilities of the page. If the bit is set, write-through caching is enabled. If not, then write-back is enabled instead.

* U/S, the ''''U'''ser/Supervisor' bit, controls access to the page based on privilege level. If the bit is set, then the page may be accessed by all; if the bit is not set, however, only the supervisor can access it. For a page directory entry, the user bit controls access to all the pages referenced by the page directory entry. Therefore if you wish to make a page a user page, you must set the user bit in the relevant page directory entry as well as the page table entry.

* R/W, the ''''R'''ead/Write'''W'''rite' permissions flag. If the bit is set, the page is read/write. Otherwise when it is not set, the page is read-only. The WP bit in CR0 determines if this is only applied to userland, always giving the kernel write access (the default) or both userland and the kernel (see Intel Manuals 3A 2-20).

Setting the SPS bit makes the page directory entry point directly to a 4-MiB page. There is no paging table involved in the address translation.

'''Note: With 4-MiB pages, whether or not bits 21 through 1213 are reserved!''' depends on PSE being enabled and how many PSE bits are supported by the processor. CPUID should be used to determine this. Thus, the physical address must also be 4-MiB-aligned. Physical addresses above 4 GiB can only be mapped using 4 MiB PDEs.