Paging: Difference between revisions
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Add 5-level paging and improve code indent
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[[image:Paging_Structure.gif|right|thumb|600x350px|x86 Paging Structure]]
Paging is a system which allows each process to see a full virtual address space, without actually requiring the full amount of physical memory to be available or present. 32-bit x86 processors support 32-bit virtual addresses and 4-GiB virtual address spaces, and current 64-bit processors support 48-bit virtual addressing and 256-TiB virtual address spaces. Intel has released [https://en.wikipedia.org/wiki/Intel_5-level_paging documentation] for a
In addition to this, paging introduces the benefit of page-level protection. In this system, user processes can only see and modify data which is paged in on their own address space, providing hardware-based isolation. System pages are also protected from user processes. On the x86-64 architecture, page-level protection now completely supersedes [[Segmentation]] as the memory protection mechanism. On the IA-32 architecture, both paging and segmentation exist, but segmentation is now considered 'legacy'.
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=== Example ===
Say the kernel is loaded to 0x100000. However, it needed to be remapped to 0xc0000000. After loading the kernel, it'll initiate paging, and set up the appropriate tables. (See [[Higher Half Kernel]]) After [[Identity Paging]] the first megabyte,it'll need to create a second table (ie. at entry #768 in the paging directory.) to map 0x100000 to
<source lang="asm">
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<source lang="C">
void *
unsigned long pdindex = (unsigned long)virtualaddr >> 22;
unsigned long ptindex = (unsigned long)virtualaddr >> 12 & 0x03FF;
unsigned long *
// Here you need to check whether the PD entry is present.
unsigned long *
// Here you need to check whether the PT entry is present.
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<source lang="C">
void map_page(void *
// Make sure that both addresses are page-aligned.
unsigned long pdindex = (unsigned long)virtualaddr >> 22;
unsigned long ptindex = (unsigned long)virtualaddr >> 12 & 0x03FF;
unsigned long *
// Here you need to check whether the PD entry is present.
// When it is not present, you need to create a new empty PT and
// adjust the PDE accordingly.
unsigned long *
// Here you need to check whether the PT entry is present.
// When it is, then there is already a mapping present. What do you do now?
pt[ptindex] = ((unsigned long)physaddr) | (flags & 0xFFF) | 0x01; // Present
// Now you need to flush the entry in the TLB
// or you might not notice the change.
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<source lang="C">
static inline void __native_flush_tlb_single(unsigned long addr) {
asm volatile("invlpg (%0)" ::"r" (addr) : "memory");
}
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=== External Links ===
*[
*[http://www.dumaisnet.ca/index.php?article=ff3b7adb128cb438ac1e306b3fbe37e7 Process Context ID]
*[https://en.wikipedia.org/wiki/Intel_5-level_paging 5-Level Paging]
[[Category:Memory management]]
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