Paging: Difference between revisions
Table 4-6, chapter 4, section 4.3 of the Intel IA64 and IA32 Architecture's Software Developer's Manual, volume 3 states that it should not necessarily be 0 if PAT is supported.
| [unchecked revision] | [unchecked revision] |
m (Link to Brendan great explains on page coloring) |
(Table 4-6, chapter 4, section 4.3 of the Intel IA64 and IA32 Architecture's Software Developer's Manual, volume 3 states that it should not necessarily be 0 if PAT is supported.) |
||
Line 42:
The first item, is once again, a 4-KiB aligned physical address. Unlike previously, however, the address is not that of a page table, but instead a 4 KiB block of physical memory that is then mapped to that location in the page table and directory.
* C, or '''C'''ached, is the 'D' bit from the previous table
* 0, if PAT is supported, shall indicate the memory type. Otherwise, it must be 0.
▲If the Dirty flag ('D') is set, then the page has been written to. This flag is not updated by the CPU, and once set will not unset itself.
=== Example ===
Say I loaded my kernel to 0x100000. However, I want it mapped to 0xc0000000. After loading my kernel, I initiate paging, and set up the appropriate tables. (See [[Higher Half Kernel]]) After [[Identity Paging]] the first megabyte, I start to create my second table (ie. at entry #768 in my directory.) to map 0x100000 to 0xc0000000. My code
<source lang="asm">
| |||