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[[image:Paging_Structure.gif|right|thumb|600x350px|x86 Paging Structure]]
 
32-bit x86 processors support a 4GiB4-GiB virtual address space and current 64 -bit processors support a 256TiB256-TiB virtual address space (with a theoretical maximum of 16EiB16 EiB). Paging is a system which allows each process to see the full virtual address space, without actually requiring the full amount of physical RAMmemory to be physicallyavailable installedor present. In fact, current implementations of x86-64 hashave a current physical RAM limit of 1TiB1 TiB and a theoretical limit of 4PiB4 PiB of physical RAM.▼
==Overview==
▲32-bit x86 processors support a 4GiB virtual address space and current 64 bit processors support a 256TiB virtual address space (with a theoretical maximum of 16EiB). Paging is a system which allows each process to see the full virtual address space, without actually requiring the full amount of physical RAM to be physically installed. In fact, current implementations of x86-64 has a current physical RAM limit of 1TiB and a theoretical limit of 4PiB of physical RAM.
 
In addition to this, paging introduces the benefit of page-level protection. In this system, user-level processes can only see and modify data which is paged in toon their own address space, providing hardware-based isolation. System pages are also protected from user processes. On the x86-64 architecture, page-level protection now completely supersedes [[Segmentation]] as the memory protection mechanism. On the IA32IA-32 architecture, both paging and segmentation exist, but segmentation is now considered 'legacy'.
 
Once an Operating System has paging, it can also make use of other benefits and workarounds, such as linear framebuffer simulation for memory-mapped IO and paging out to disk, where disk storage space is used to free up physical RAM.
 
==MMU==
Paging is achieved through the use of the MMU (temporary: [[MMU|article 1]], [[Memory Management Unit|article 2]]). The MMU is a unit that transforms virtual addresses into physical addresses based on the current page table.This section focuses on the x86 MMU.▼
 
▲Paging is achieved through the use of the MMU (temporary: [[MMU|article 1]], [[Memory Management Unit|article 2]]). TheOn MMUthe isx86, athe unitMMU thatmaps transformsmemory virtualthrough addressesa intoseries physicalof addressestables, basedtwo onto thebe currentexact. pageThey table.Thisare sectionthe focusespaging ondirectory (PD), and the x86paging MMUtable (PT).
===Overview===
On the x86, the MMU maps memory through a series of tables, two to be exact. They are the paging directory, and the paging table.
 
Both tables contain 1024 4byte4-byte entries, making them each4 4kbKiB each. In the page directory, each entry points to a page table. In the page table, each entry points to a physical address that is then mapped to the virtual address found by calculating the offset within the directory and the offset within the table. This can be done as the entire table system represents a linear 4gb4-GiB virtual memory map.
 
===Page Directory===
The topmost paging structure is the page directory. It is essentially an array of page directory entries that take the following form.
 
'''Note: With 4mb pages, bits 21 through 12 are Reserved!'''▼
 
[[Image:Page dir.png|frame|A Page Directory Entry]]
 
The page table address field represents the physical address of the page table that manages the four megabytes at that point. Please note that it is very important that this address be 4 -KiB aligned. This is needed, due to the fact that the last 12 bits of the 32-bit value are overwritten by access bits and such.
 
* S, or 'Page '''S'''ize' stores the page size for that specific entry. If the bit is set, then pages are 4 MiB in size. Otherwise, they are 4 KiB. Please note that for 4 -MiB pages require PSE have to be enabled.
* A, or ''''A'''ccessed' is used to discover whether a page has been read or written to. If it has, then the bit is set, otherwise, it is not. Note that, this bit will not be cleared by the CPU, so that burden falls on the OS (if it needs this bit at all).
* D, is the 'Cache '''D'''isable' bit. If the bit is set, the page will not be cached. Otherwise, it will be.
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The remaining bits 9 through 11 are not used by the processor, and are free for the OS to store some of its own accounting information. In addition, when P is not set, the processor ignores the rest of the entry and you can use all remaining 31 bits for extra information, like recording where the page has ended up in swap space.
 
Setting the S bit makes the page directory entry point directly to a 4-MiB page. There is no paging table involved in the address translation.
▲'''Note: With 4mb4-MiB pages, bits 21 through 12 are Reservedreserved!''' Thus, the physical address must also be 4-MiB-aligned.
 
===Page Table===
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The 'C' bit is 'D' bit above.
 
====INVLPG====▼
 
INVLPG is an instruction available since the 486 that invalidates a single page table entry in the TLB. Intel notes that this instruction may be implemented differently on future processes, but that this alternate behavior must be explicitly enabled. INVLPG modifies no flags.▼
 
NASM example:▼
<source lang="C">▼
invlpg [0]▼
</source>▼
 
Inline asm in GCC (from Linux kernel source):▼
<source lang="C">▼
static inline void __native_flush_tlb_single(unsigned long addr)▼
{▼
asm volatile("invlpg (%0)" ::"r" (addr) : "memory");▼
}▼
</source>▼
 
===Example===
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When the CPU fires a page-not-present exception the CR2 register is populated with the linear address that caused the exception. The upper 10 bits specify the page directory entry (PDE) and the middle 10 bits specify the page table entry (PTE). First check the PDE and see if it's present bit is set, if not setup a page table and point the PDE to the base address of the page table, set the present bit and iretd. If the PDE is present then the present bit of the PTE will be cleared. You'll need to map some physical memory to the page table, set the present bit and then iretd to continue processing.
 
▲====INVLPG====
 
▲INVLPG is an instruction available since the 486i486 that invalidates a single page table entry in the TLB. Intel notes that this instruction may be implemented differently on future processes, but that this alternate behavior must be explicitly enabled. INVLPG modifies no flags.
 
▲NASM example:
▲<source lang="C">
▲ invlpg [0]
▲</source>
 
▲Inline asm in GCC (from Linux kernel source):
▲<source lang="C">
▲static inline void __native_flush_tlb_single(unsigned long addr)
▲{
▲ asm volatile("invlpg (%0)" ::"r" (addr) : "memory");
▲}
▲</source>
 
==Paging Tricks==
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