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For memory efficiency, two or more processes can share pages as read-only. If one process were to write to its page, then a page fault would occur and the system could duplicate the page and then mark it as read-write. This is known as copy-on-write (COW). Copy-on-write allows the system to delay memory allocation until a process actually requires it, preventing unnecessary copying.
== PAT ==
The Page Attribute Table determines caching attributes on a page granularity. This is similar to [[MTRR]]s, but those apply to physical addresses and are more limited.
The PAT is set via the IA32_PAT_MSR [[MSR]] (0x277). It has 8 entries, taking the low order 3 bits of each byte, in standard little endian order. So the high byte is PAT7, low byte is PAT0.
The following are the different caching types.
{| class="wikitable" border="1"
|-
! Number
! Name
! Description
|-
| 0
| UC — Uncacheable
| All accesses are uncacheable. Write combining is not allowed. Speculative accesses are not allowed.
|-
| 1
| WC — Write-Combining
| All accesses are uncacheable. Write combining is allowed. Speculative reads are allowed.
|-
| 4
| WT — Writethrough
| Reads allocate cache lines on a cache miss. Cache lines are not allocated on a write miss.
Write hits update the cache and main memory.
|-
| 5
| WP — Write-Protect
| Reads allocate cache lines on a cache miss. All writes update main memory.
Cache lines are not allocated on a write miss. Write hits invalidate the cache
line and update main memory.
|-
| 6
| WB — Writeback
| Reads allocate cache lines on a cache miss, and can allocate to either the shared,
exclusive, or modified state. Writes allocate to the modified state on a cache miss.
|-
| 7
| UC- — Uncached
| Same as uncacheable, ''except'' that this can be overriden by Write-Combining MTRRs.
|}
The PAT has a reset value of 0x0007040600070406. This ensures compatibility with non-PAT usage. This corresponds to the following:
{| class="wikitable" border="1"
|-
|UC
|UC-
|WT
|WB
|UC
|UC-
|WT
|WB
|}
The PAT is indexed by the three page table bits:
{| class="wikitable" border="1"
|-
|PAT
|PCD
|PWT
|}
The PAT bit is reserved when there isn't a PAT, and the default value of the MSR ensures backwards comaptibility with the PCD and PWT bit.
You will need to modify the PAT if you want Write-Combining cache, which is very useful for framebuffers.
== See Also ==
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