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Added a relaxed MMU\Page Structure overview
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==MMU==
Paging is achieved through the use of the [[MMU]].
===Relaxed Technical Overview===
Think of your RAM. It is probably several hundred megabytes of continuous non-volatile memory. Now, imagine that it is actually 4 gigabytes. This is what the MMU is paid to do with a little help from the kernel.
In a 32bit Intel x86 CPU, there are 2 types of tables. There are the:
i* Page Directory
* Page Tables
Knowing this, there are some simple rules, if you will:
* There is only one page directory in use at any one time.
* Each structure consumes 4kb of space.
* Each entry in each structure is 4bytes in size.
If you will recall, we know that the MMU is made to map x number of megabytes to 4 gigabytes. Considering this, we can now figure out how physical memory is mapped.
*page directory size = 4096 bytes
*page entry = 4 bytes
*number of directory entries = 4096/4 = 1024
*number of table entries = directory entries = 1024
*mapped RAM per directory entry (aka. a table) = 4gb/1024 = 4mb
*mapped RAM per table entry (aka. a page) = 4mb/1024 = 4kb.
There you have it. Each 'page' is then 4kb.
The structure of the above in computer speak is quite simple. Each entry is the address of it's child. If it's a directory entry, the entry consists of the table's address. Moreover, if it's a table's entry we're talking about, then it's the the address of the mapped physical memory.
A short note, however, just to ruin your simplicity. Each entry described above also contains 3 flags on the least significant bits. The full layout is as follows:
*Bits 31-3: 4kb aligned address of entry
*Bit 2: Modified flag - Pages with this set must be copied to disk before deletion.
*Bit 1: Used Flag - While set, the MMU assumes that this page is actively mapped to some physical address.
*Bit 0: Presence Flag - While set, the MMU will assume that this page is currently in memory.
Have you made the connection? Each page is 4kb, and each entry's address must be 4kb aligned! It's just clicking, isn't it?
====Example====
Say I loaded my kernel to 0x100000. However, I want it mapped to 0xc0000000. After loading my kernel, I initiate paging, and set up the appropriate tables. (See [[Higher Half Kernel]]) After [[Identity Paging]] the first megabyte, I start to create my second table (ie. at entry #768 in my directory.) to map 0x100000 to 0xc0000000. My code could be like:
mov eax, 0x0
mov ebx, 0x100000
.fill_table:
mov ecx, ebx
or ecx, 3
mov [table_768+eax*4], ecx
add ebx, 4096
inc eax
cmp eax, 1024
je .end
jmp .fill_table
.end:
==Enabling==
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